ST62E40B STMICROELECTRONICS [STMicroelectronics], ST62E40B Datasheet
ST62E40B
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ST62E40B Summary of contents
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... ST6240-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY OTP EPROM DEVICE (Bytes) (Bytes) ST62T40B 7948 - ST62E40B 7948 August 1999 ST62T40B/E40B EEPROM AND A/D CONVERTER with 7-bit (See end of Datasheet for Ordering Information) I/O Pins PQFP80 CQFP80W Rev ...
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ST62T40B/E40B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 ...
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LCD alternate functions (combiports ...
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ST6240B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... EPROM/OTP versions only) PP common core is surrounded by a number of on- chip peripherals. The ST62E40B is the erasable EPROM version of the ST62T40B device, which may be used to em- ulate the ST62T40B device, as well as the respec- tive ST6240B ROM devices. PORT A 8-BIT PORT B PORT C ...
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ST62T40B/E40B INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions.OTP devices offer all ...
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PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are internally connected ...
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ST62T40B/E40B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code ...
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... MEMORY MAP (Cont’d) Table 2. ST62E40B/T40B Program Memory Map ROM Page Device Address Description 0000h-007Fh Page 0 0080h-07FFh User ROM 0800h-0F9Fh User ROM 0FA0h-0FEFh Page 1 0FF0h-0FF7h Interrupt Vectors “STATIC” 0FF8h-0FFBh 0FFCh-0FFDh NMI Vector 0FFEh-0FFFh Reset Vector 0000h-000Fh Page 2 0010h-07FFh User ROM ...
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... Program memory. 1.3.3.2 Data RAM/EEPROM In ST62T40B and ST62E40B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the pe- ...
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MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data Read-Only Memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, be- tween address ...
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ST62T40B/E40B MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM Bank (DRBR) Address: CBh — Write only DRBR4 DRBR3 - Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page ...
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MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in ...
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ST62T40B/E40B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write ...
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... The erasure time with this dosage is ap- proximately minutes using an ultraviolet lamp with 12000 W/cm ST62E40B should be placed within 2.5cm (1Inch) of the lamp tubes during erasure. ST62T40B/E40B pin. The PP 2 power rating. The ...
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ST62T40B/E40B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ...
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CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...
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ST62T40B/E40B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 Main Oscillator The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or ...
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CLOCK SYSTEM (Cont’d) 3.1.2 32 KHz STAND-BY OSCILLATOR An additional 32KHz stand-by on chip oscillator al- lows to generate real time interrupts and to supply the clock to the LCD driver with the main oscillator stopped. This enables the MCU ...
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ST62T40B/E40B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be ...
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RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...
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ST62T40B/E40B RESETS (Cont’d) Table 8. Register Reset Status Register EEPROM Control Register 0DFh Port Data Registers 0C0h, 0C2h, 0C3h Port A,B Direction Register 0C4h to 0C5h Port A,B Option Register 0CCh, 0CEh Interrupt Option Register 0C8h SPI Registers 0C2h to ...
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DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset ...
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ST62T40B/E40B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR). This register is set to 0FEh on ...
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DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110b Bit Watchdog Control bit If the hardware option is selected, this bit is forced ...
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ST62T40B/E40B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 ...
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INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated ...
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ST62T40B/E40B INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the ...
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... STOP/WAIT 0 modes. This register is cleared on reset 3.4.4 Interrupt sources Interrupt sources ST62E40B/T40B are summarized in the Table 12 with associated mask bit to enable/disable the in- terrupt request. Address Mask bit Masked Interrupt Source Register All Interrupts, excluding NM GEN ETI ...
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ST62T40B/E40B INTERRUPTS (Cont’d) Figure 17. Interrupt Block Diagram PIF PSS PEI NMI SPI FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B PORT C PBE Bits TIMER1 TIMER2 OSCEOC OSC32kHz EOSCI A/D CONVERTER 30/72 ...
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POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following ...
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ST62T40B/E40B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart ...
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ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with ...
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ST62T40B/E40B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). ...
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I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated ...
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ST62T40B/E40B I/O PORTS (Cont’d) Table 14. I/O Port configuration for the ST62T40B/E40B MODE AVAILABLE ON PA0-PA7 Input PB0-PB7 PC0-PC7 Input PA0-PA7 with pull up PB0-PB7 (Reset state except for PC0-PC7 PC0-PC7) Input PA0-PA7 with pull up PB0-PB7 with interrupt PC0-PC7 ...
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I/O PORTS (Cont’d) 4.1.3 LCD alternate functions (combiports) PC0 to PC7 can also be individually defined as 8 LCD segment output by setting DDRC, ORC and DRC registers as shown in Table 15. On the contrary with other I/O lines, ...
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ST62T40B/E40B I/O PORTS (Cont’d) 4.1.5 I/O Port Option Registers ORA/B/C (CCh PA, CDh PB, CFh PC) Read/Write 7 Px7 Px6 Px5 Px4 Px3 Px2 Bit 7-0 = Px7 - Px0: Port Option Register bits. 4.1.6 I/O Port ...
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TIMER 1 & 2 The MCU features two on-chip Timer peripheral named TIMER 1 & TIMER 2. Each of these timers consist of an 8-bit counter with a 7-bit programma- ble prescaler, giving a maximum count of 2 Figure ...
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ST62T40B/E40B Figure 22. TIMER 1 Block Diagram PSC TIMER Figure 23. TIMER 2 Block Diagram PSC INT 40/72 40 DATABUS 8 8 ...
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TIMER 1& 2 (Cont’d) 4.2.1 TIMER 1 Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to ...
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ST62T40B/E40B TIMER 1& 2 (Cont’d) 4.2.5 TIMER 1 Registers Timer Status Control Register (TSCR) Address: 0D4h — Read/Write 7 TMZ ETI TOUT DOUT PSI PS2 Bit 7 = TMZ: Timer Zero bit A low-to-high transition indicates that the timer count ...
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TIMER 1& 2 (Cont’d) 4.2.6 TIMER 2 Registers Timer Status Control Register (TSCR) Address: 0D7h — Read/Write 7 TMZ ETI D5 D4 PSI PS2 Bit 7 = TMZ: Timer Zero bit A low-to-high transition indicates that the timer count register ...
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ST62T40B/E40B 4.3 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time ...
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A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply ...
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ST62T40B/E40B 4.4 SERIAL PERIPHERAL INTERFACE (SPI) The on-chip SPI is an optimized serial synchro- nous interface that supports a wide range of indus- try standard SPI specifications. The on-chip SPI is controlled by small and simple user software to perform ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) After 8 clock pulses (D7..D0) the output Q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. Q4 enables the clock to generate an interrupt on the 8th ...
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ST62T40B/E40B 4.5 LCD CONTROLLER-DRIVER On-chip LCD driver includes all features required for LCD driving, including multiplexing of the com- mon plates. Multiplexing allows to increase display capability without increasing the number of seg- ment outputs. In that case, the display ...
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LCD CONTROLLER-DRIVER (Continued) 4.5.1 Multiplexing ratio and frame frequency setting common plates COM1..COM4 can be used for multiplexing ratio ranging from 1/1 to 1/4. The selection is made by the bits DS0 and DS1 of the LCDCR ...
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ST62T40B/E40B LCD CONTROLLER-DRIVER (Continued) Figure 29. Typical Network to connect to V pins if V 4.5V LCD V LCD R V LCD2 LCD1 100k C: 47nF Figure 30. Addressing Map of the LCD RAM ...
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LCD CONTROLLER-DRIVER (Continued) 4.5.4 Stand by or STOP operation mode No clock from the main oscillator is available in STOP mode for the LCD controller, and the con- troller is switched off when the STOP instruction is executed. All segment ...
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ST62T40B/E40B 4.6 POWERSUPPLY SUPERVISOR DEVICE (PSS) The Power Supply Supervisor device, described in the Figure 32, permits supervising the crossing of the PSS pin voltage (VPSS) through a program- mable voltage (mxV /n), where n and m can be DD ...
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POWER SUPPLY SUPERVISOR (Continued) 4.6.1 PSS Operating Mode Description The resistive voltage divider connected to the PSS pin provides the internal comparator with the nxV /13 voltage. The resistive voltage divider PSS connected to the V pin provides the internal ...
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ST62T40B/E40B POWER SUPPLY SUPERVISOR (Continued) 4.6.2 PSS Register The PSS register permits control over the PSS de- vice. The register can be addressed in the data space as a RAM location at DAh. This register is cleared after Reset. PSS ...
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SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core ...
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ST62T40B/E40B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control ...
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INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space ...
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ST62T40B/E40B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets ...
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 0010 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ ...
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ST62T40B/E40B Opcode Map Summary (Continued) LOW 8 9 1000 1001 1010 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 ...
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ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...
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ST62T40B/E40B 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken ...
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DC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All ...
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ST62T40B/E40B 6.4 AC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter (1) t Supply Recovery Time REC Minimum Pulse Width ( RESET pin WR NMI pin T EEPROM Write Time WEE Endurance ...
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TIMER CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter f Input Frequency on TIMER Pin Pulse Width at TIMER Pin* W Note*: When available. 6.7 SPI CHARACTERISTICS (T = -40 to +85 ...
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ST62T40B/E40B 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 35. 80-Pin Plastic Quad Flat Package Figure 36. 80-Pin Ceramic Quad Flat Package 66/72 66 Dim Min A A1 0.25 A2 2.55 2.80 3.05 0.100 0.110 0.120 B 0.30 C 0.13 ...
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... GENERAL INFORMATION (Cont’d) 7.2 PACKAGE THERMAL CHARACTERISTIC Symbol Parameter RthJA Thermal Resistance 7.3 .ORDERING INFORMATION Table 32. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62E40BG1 7948 (EPROM) ST62T40BQ6 7948 (OTP) Value Test Conditions Min. Typ. PQFP80 CQFP80W I/O Temperature Range ...
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ST62T40B/E40B Notes: 68/72 68 ...
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Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size ...
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ST6240B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6240B is mask programmed ROM version of ST62T40B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP ...
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ST6240B MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . . . ...
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ST6240B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options. ...