TBS6416B4E-7G ETC2 [List of Unclassifed Manufacturers], TBS6416B4E-7G Datasheet

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TBS6416B4E-7G

Manufacturer Part Number
TBS6416B4E-7G
Description
1M x 16Bit x 4 Banks synchronous DRAM
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet

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Part Number:
TBS6416B4E-7G
Quantity:
73
M
1M x 16Bit x 4 Banks synchronous DRAM
GENERAL DESCRIPTION
The TBS6416B4E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,
fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four-banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
ORDERING INFORMATION
Revision_1.1
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
.tec
TBS6416B4E-7G
Part No.
Max Freq.
143MHz
Interface
LVTTL
1
TwinMOS Technologies Inc.
Package
TSOP(II)
54
TBS6416B4E
Sep. 2000

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TBS6416B4E-7G Summary of contents

Page 1

... All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) ORDERING INFORMATION Part No. TBS6416B4E-7G Revision_1.1 Max Freq. Interface 143MHz LVTTL TwinMOS Technologies Inc. ...

Page 2

... M .tec (Top View) PIN CONFIGURATION Revision_1.1 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) TwinMOS Technologies Inc. 2 TBS6416B4E Sep. 2000 ...

Page 3

... Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from , used for output buffers to improve noise. VCC Separated ground from , used for output buffers to improve noise. VSS No connection TwinMOS Technologies Inc. 3 TBS6416B4E Sep. 2000 ...

Page 4

... Commend / RAS Decoder / CAS & Clock Buffer CLK CKE Revision_1.1 Bank Select Data Input Row Decoder 1Mx16 & 1Mx16 Refresh Counter 1Mx16 1Mx16 Column Decoder Column Buffer Latency & Burst Length Programming Register TwinMOS Technologies Inc. 4 TBS6416B4E Output Buffer DQ Sep. 2000 ...

Page 5

... Q T STG 0V 70° Symbol Min Typ VCC, VCC 3.0 3 2 TwinMOS Technologies Inc. 5 TBS6416B4E Value Unit -1.0 ~ 4.6 V -1.0 ~ 4.6 V -55 ~ +150 ℃ Max Unit 3.6 V VCC + 1.5 uA Note =-2mA ...

Page 6

... Input signals are stable Page burst I CC4 2Banks activated 2CLK CCD (min) I RC≧ RC CC5 CKE≦0.2V I CC6 TwinMOS Technologies Inc. 6 TBS6416B4E-7G 100 2 = ∞ 2 (min (Max ∞ 5 (min (Max 150 140 160 1 TBS6416B4E Unit Note ...

Page 7

... Output Data Hold Time Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time Revision_1.1 TBS6416B4E-7G Symbol Min t 14 RRD t 20 RCD ...

Page 8

... ITEM TwinMOS Technologies Inc. 8 TBS6416B4E detail of lead end MILLIMETERS INCHES 22.62 MAX. 0.891 MAX. 0.91 MAX. 0.036 MAX. 0.80 (T.P.) 0.031 (T.P.) +0.08 0.32 0.013±0.003 –0.07 0.10±0.05 0.004±0.002 1.20 MAX. 0.048 MAX. ...

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