ADR395 AD [Analog Devices], ADR395 Datasheet - Page 31

• Manufacturer Part Number: ADR395
• Description: Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
When data is being transmitted to the AD5762R, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 24-bit word, PC7 is not brought high
until the third 8-bit word has been transferred to the DACs
input shift register.
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 3-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. For
example, if CLR were used, it could be controlled by port
output PC5.
AD5762R to 8XC51 Interface
The AD5762R requires a clock synchronized to the serial data.
For this reason, the 8XC51 must be operated in Mode 0. In this
mode, serial data enters and exits through RXD, and a shift
clock is output on TXD.
P3.3 and P3.4 are bit programmable pins on the serial port and
are used to drive SYNC and LDAC , respectively. The 8CX51
provides the LSB of its SBUF register as the first bit in the data
stream. The user must ensure that the data in the SBUF register
is arranged correctly, because the DAC expects MSB first. When
data is to be transmitted to the DAC, P3.3 is taken low. Data on
RXD is clocked out of the microcontroller on the rising edge of
TXD and is valid on the falling edge. As a result, no glue logic is
required between this DAC and the microcontroller interface.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
MC68HC11
8XC51
Figure 44. AD5762R to MC68HC11 Interface
Figure 45. AD5762R to 8XC51 Interface
MISO
MOSI
1
SCK
RxD
P3.3
P3.4
PC7
TxD
1
SDO
SDIN
SCLK
SYNC
SDIN
SCLK
SYNC
LDAC
AD5762R
AD5762R
1
1
Rev. PrA | Page 31 of 33
The 8XC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 24-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the third byte has been
transferred, the P3.3 line is taken high. The DAC can be
updated using LDAC via P3.4 of the 8XC51.
AD5762R to ADSP2101/ADSP2103 Interface
An interface between the AD5762R and the ADSP2101/
ADSP2103 is shown in Figure 46. The ADSP2101/ ADSP2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP2101/ADSP2103 are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and 24-
bit word length.
Transmission is initiated by writing a word to the TX register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alterna-
tively, the LDAC input could be tied permanently low, and then
the update takes place automatically when TFS is taken high.
AD5762R to PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5762R. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
needed. Figure 47 shows the connection diagram.
1
ADDITIONAL PINS OMITTED FOR CLARITY
ADSP2101/
ADSP2103
Figure 46. AD5762R to ADSP2101/ADSP2103 Interface
SCLK
RFS
TFS
DR
FO
DT
1
SDO
SDIN
SCLK
SYNC
LDAC
AD5762R
AD5762R
1