ADR435 AD [Analog Devices], ADR435 Datasheet - Page 39

• Manufacturer Part Number: ADR435
• Description: Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output
• Manufacturer: AD [Analog Devices]

Data Sheet
DEVICE FEATURES
FAULT OUTPUT
The
open-drain output that allows several
connected together to one pull-up resistor for global fault
detection. The FAULT pin is forced active by any one of the
following fault conditions:
•
•
•
•
The V
of the status register are used in conjunction with the FAULT
output to inform the user which fault condition caused the
FAULT output to be activated.
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION
Under normal operation, the voltage output sinks/sources up
to 12 mA and maintains specified operation. The maximum
output current or short-circuit current is programmable by
the user and can be set to 16 mA or 8 mA. If a short circuit is
detected, the FAULT pin goes low, and the relevant V
bit is set in the status register (see Table 33).
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the DAC data register is
operated on by a digital multiplier and adder controlled by the
contents of the gain and offset registers; the calibrated DAC
data is then stored in the DAC input register (see Figure 75).
AD5735
The voltage at I
range due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with windowed
limits because this requires an actual output error before
the FAULT output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive
capability. Thus, the FAULT output is activated slightly
before the compliance limit is reached.
A short circuit is detected on a voltage output pin. The
short-circuit current is limited to 16 mA or 8 mA, which
is programmable by the user. If the
polar supply mode, a short-circuit fault may be generated
if the output voltage is below 50 mV.
An interface error is detected due to a PEC failure (see the
Packet Error Checking section).
The core temperature of the
mately 150°C.
OUT_x
fault, I
is equipped with a FAULT pin, an active low,
OUT_x
OUT_x
fault, PEC error, and over temp bits
attempts to rise above the compliance
AD5735
AD5735
AD5735
exceeds approxi-
devices to be
is used in uni-
OUT_x
fault
Rev. B | Page 39 of 48
Although Figure 75 indicates a multiplier and adder for each
channel, the device has only one multiplier and one adder,
which are shared by all four channels. This design has impli-
cations for the update speed when several channels are updated
at once (see Table 3).
When data is written to the gain (M) or offset (C) register, the
output is not automatically updated. Instead, the next write to
the DAC channel uses the new gain and offset values to perform
a new calibration and automatically updates the channel.
The output data from the calibration is routed to the DAC input
register. This data is then loaded to the DAC, as described in the
Serial Interface section. Both the gain register and the offset
register have 12 bits of resolution. The correct order to calibrate
the gain and offset is to first calibrate the gain and then calibrate
the offset.
The value (in decimal) that is written to the DAC input register
can be calculated as follows:
where:
D is the code loaded to the DAC data register of the
DAC channel.
M is the code in the gain register (default code = 2
C is the code in the offset register (default code = 2
STATUS READBACK DURING A WRITE
The
the status register during every write sequence. This feature is
enabled using the STATREAD bit in the main control register.
When this feature is enabled, the user can continuously monitor
the status register and act quickly in the case of a fault.
When status readback during a write is enabled, the contents
of the 16-bit status register (see Table 33) are output on the SDO
pin, as shown in Figure 5.
When the
write feature is disabled. When this feature is enabled, readback
of registers other than the status register is not available. To read
back any other register, clear the STATREAD bit before following
the readback sequence (see the Readback Operation section).
The STATREAD bit can be set high again after the register read.
AD5735
Code
OFFSET (C)
DAC DATA
REGISTER
REGISTER
REGISTER
DACRegiste
GAIN (M)
AD5735
can be configured to read back the contents of
Figure 75. Digital Offset and Gain Control
r
=
is powered up, the status readback during a
D
×
(
M
2
12
+
) 1
+
C
REGISTER
INPUT
−
DAC
2
11
12
11
DAC
AD5735
− 1).
).
(1)