SAM3A ATMEL [ATMEL Corporation], SAM3A Datasheet
SAM3A
Related parts for SAM3A
SAM3A Summary of contents
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... LQFP mm, pitch 0.5 mm – 100-ball LFBGA mm, pitch 0.8 mm – 144-lead LQFP mm, pitch 0.5 mm – 144-ball LFBGA mm, pitch 0.8 mm ® , Flow Control, SPI, Manchester and LIN support) AT91SAM ARM-based Flash MCU SAM3X SAM3A Series Summary 11057BS–ATARM–13-Jul-12 ...
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SAM3X/A Description Atmel’s SAM3X/A series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 84 MHz and features up to 512 Kbytes ...
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... Mode channels are accessible through PIO channels are accessible through PIO channels are accessible through PIO 7. USART3 in UART mode (RXD3 and TXD3 available) SAM3X4C SAM3A8C SAM3A4C 2 x 128 Kbytes 2 x 256 Kbytes 2 x 128 Kbytes Kbytes - - - ...
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... SAM3X/A Block Diagram Figure 2-1. SAM3A4/8C (100 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC XOUT WDT RC 12/8/4 M FWUP XIN32 XOUT32 ERASE VDDBU VDDCORE VDDUTMI NRST PIOA PIOC TWCK0 TWD0 TWCK1 TWD1 URXD UTXD TXD0 SCK0 RTS0 CTS0 RXD1 ...
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Figure 2-2. SAM3X4/8C (100 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC 12M XOUT WDT RC 12/8/4 M FWUP XIN32 XOUT32 ERASE VDDBU VDDCORE VDDUTMI NRST PIOA PIOC TWCK0 TWD0 TWCK1 TWD1 URXD UTXD RXD0 TXD0 SCK0 ...
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Figure 2-3. SAM3X4/8E (144 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC XOUT WDT RC 12/8/4 M SHDN SUPC FWUP XIN32 OSC 32K XOUT32 RC 32K ERASE GPBREG NRSTB VDDBU VDDCORE RSTC VDDUTMI NRST PIOA PIOC PIOE ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIO Peripherals I/O Lines Power Supply VDDUTMI USB UTMI+ Interface Power Supply VDDOUT Voltage Regulator Output Voltage Regulator, ADC and DAC Power VDDIN Supply GNDUTMI USB UTMI+ ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TCK/SWCLK Test Clock/Serial Wire Clock TDI Test Data In Test Data Out / Trace Asynchronous Data TDO/TRACESWO Out Test Mode Select /Serial Wire TMS/SWDIO Input/Output JTAGSEL JTAG Selection Flash and NVM ...
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Table 3-1. Signal Description List (Continued) Signal Name Function PA0 - PA31 Parallel IO Controller A PB0 - PB31 Parallel IO Controller B PC0 - PC30 Parallel IO Controller C PD0 - PD30 Parallel IO Controller D PE0 - PE31 ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDRDY NAND Ready NANDCLE NAND Flash Command Line Enable NANDALE NAND Flash Address Line Enable MCCK Multimedia Card Clock MCCDA Multimedia ...
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Table 3-1. Signal Description List (Continued) Signal Name Function CANRXx CAN Input CANTXx CAN Output TD SSC Transmit Data RD SSC Receive Data TK SSC Transmit Clock RK SSC Receive Clock TF SSC Transmit Frame Sync RF SSC Receive Frame ...
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... In order to facilitate schematic capture when using a SAM3X/A design, Atmel provides a “Sche- matics Checklist” Application Note. See 4. Package and Pinout 4.1 SAM3A4/8C and SAM3X4/8C Package and Pinout The SAM3A4/8C and SAM3X4/8C are available in 100-lead LQFP and 100-ball LFBGA packages. SAM3X/A SAM3X ...
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LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline Figure 4-2. 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 Orientation of the 100-lead LQFP Package 75 76 100 1 Orientation of the 100-ball LFBGA Package TOP VIEW ...
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... LQFP Pinout Table 4-1. 100-lead LQFP SAM3A4/8C and SAM3X4/8C Pinout 1 PB26 2 PA9 3 PA10 4 PA11 5 PA12 6 PA13 7 PA14 8 PA15 9 PA17 10 VDDCORE 11 VDDIO 12 GND 13 PA0 14 PA1 15 PA5 16 PA7 17 PA8 18 PB28 19 PB29 20 PB30 21 PB31 22 GNDPLL 23 VDDPLL 24 XOUT 25 XIN SAM3X/A SAM3X DHSDP 51 27 DHSDM ...
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LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3X4/8E Package and Pinout A1 PB26 A2 PB24 A3 PB22 A4 PB14 A5 PC0 A6 PB9 A7 PB6 A8 PB2 A9 PA28 A10 PA26 B1 PA11 B2 PB25 B3 PB23 B4 PA10 ...
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SAM3X4/8E Package and Pinout The SAM3X4/8E is available in 144-lead LQFP and 144-ball LFBGA packages. 4.2.1 144-lead LQFP Package Outline Figure 4-3. Orientation of the 144-lead LQFP Package 4.2.2 144-ball LFBGA Package Outline The 144-Ball LFBGA package has a ...
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LQFP Pinout Table 4-3. 144-lead LQFP SAM3X4/8E Pinout 1 PB26 2 PA9 3 PA10 4 PA11 5 PA12 6 PA13 7 PA14 8 PA15 9 PA17 10 VDDCORE 11 VDDIO 12 GND 13 PD0 14 PD1 15 PD2 ...
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LFBGA Pinout Table 4-4. 144-ball LFBGA SAM3X4/8E Pinout A1 PA9 A2 PB23 A3 PB14 A4 PC26 A5 PC24 A6 PC20 A7 PB10 A8 PB6 A9 PB4 A10 PC4 A11 PA28 A12 PA27 B1 PA10 B2 PB26 B3 PB24 ...
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Power Considerations 5.1 Power Supplies The SAM3X/A series product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the ...
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Typical Powering Schematics The SAM3X/A series supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. schematics. Figure 5-1. Note: SAM3X/A SAM3X Single Supply Main Supply (1.8V-3.6V) Restrictions ...
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Figure 5-2. Note: 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 Core Externally Supplied Main Supply (1.62V-3.6V) VDDCORE Supply (1.62V-1.95V) Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater ...
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Note: Note: 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...
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The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz Oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup Mode is based on ...
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The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode. 5.5.4 Low Power Mode Summary Table The modes detailed ...
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Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-3. Wake-up Source SMEN sm_int RTCEN ...
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Fast Start-Up The SAM3X/A series allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up ...
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Input/Output Lines The SAM3X/A has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same PIO line can be ...
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Table 6-1. System I/O Configuration Pin List SYSTEM_IO Default Function Bit Number Peripheral After Reset TCK/SWCLK A A TDO/TRACESWO A TMS/SWDIO Note: 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, ...
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NRST Pin The NRST pin is bidirectional handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It will ...
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... Full datasheet for further details. 7.3 Matrix Masters The Bus Matrix of the SAM3X/A series product manages 5 (SAM3A (SAM3X) masters, which means that each master can perform an access, concurrently with others available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all masters have the same decodings ...
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Matrix Slaves The Bus Matrix of the SAM3X/A series product manages 9 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave ...
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... DMA Controller • Acting as one Matrix Master • Embeds 4 (SAM3A and 100-pin SAM3X (144-pin SAM3X) channels Table 7-4. 8 bytes FIFO for Channel Buffering 32 bytes FIFO for Channel Buffering • Linked List support with Status Write Back operation at End of Transfer • Word, HalfWord, Byte transfer support. ...
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Peripheral DMA Controller • Handles data transfer between peripherals and memories • Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from ...
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Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset • Serial Wire Debug Port (SW-DP) and Serial Wire JTAG ...
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Product Mapping Figure 8-1. SAM3X/A Product Mapping Code Boot Memory Internal Flash 0 Internal Flash 1 Internal ROM Reserved HALF_FLASHSIZE address: - 512ko products: 0x000C0000 - 256k products: 0x000A0000 - 128k products: 0x00090000 SRAM SRAM0 SRAM1 NFC (SRAM) UOTGHS ...
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... Flash Overview • The Flash of the ATSAM3A/X8 is organized in two banks of 1024 pages (dual plane) of 256 bytes. • The Flash of the ATSAM3A/X4 is organized in two banks of 512 pages (dual plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 9.1.3.2 Flash Power Supply The Flash is supplied by VDDCORE ...
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The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the ...
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The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 ...
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The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 9.1.3.10 GPNVM Bits The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through ...
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External Memories The 144-pin SAM3X features one External Memory Bus to offer interface to a wide range of external memories and to any parallel peripheral. 9.2.1 External Memory Bus • Integrates Four External Memory Controllers: – Static Memory Controller ...
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System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers allowing ...
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Figure 10-1. System Controller Block Diagram VDDBU FWUP SHDN NRSTB Zero-Power Power-on Reset General Purpose Backup Registers SLCK RTC SLCK RTT osc32k_xtal_en XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC osc32k_rc_en Oscillator Backup Power Supply vddcore_nreset NRST FSTT0 ...
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System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3X/A embeds three features to monitor, ...
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The Slow Clock generator is based kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the ...
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Figure 10-2. Clock Generator Block Diagram 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock HCLK • the Free running processor clock FCLK • the Cortex SysTick ...
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Figure 10-3. The SysTick calibration value is fixed at 10500, which allows the generation of a time base with SystTick clock to 10.5 MHz (max HCLK/8). 10.7 Watchdog Timer • 16-bit key-protected once-only Programmable Counter • Windowed, ...
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... Table 10-1. ATSAM3X8H (Rev A) ATSAM3X8E (Rev A) ATSAM3X4E (Rev A) ATSAM3X8C (Rev A) ATSAM3X4C (Rev A) ATSAM3A8C (Rev A) ATSAM3A4C (Rev A) 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 restoration between interrupts. ATSAM3A/X Chip IDs Register Chip Name CHIPID_CIDR 0x286E0A60 0x285E0A60 0x285B0960 0x284E0A60 0x284B0960 0x283E0A60 0x283B0960 SAM3X/A ...
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UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun ...
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Peripherals 11.1 Peripheral Identifiers Table 11-1 required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always ...
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... CAN1 11.2 Peripheral Signal Multiplexing on I/O Lines The SAM3X/A series product features 3 PIO (SAM3A and 100-pin SAM3X PIO (144-pin SAM3X) controllers, PIOA, PIOB, PIOC, PIOD, PIOE and PIOF, which multiplexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The column “ ...
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PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A PA0 CANTX0 PA1 CANRX0 PA2 TIOA1 PA3 TIOB1 PA4 TCLK1 PA5 TIOA2 PA6 TIOB2 PA7 TCLK2 PA8 URXD PA9 UTXD PA10 RXD0 PA11 ...
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... PB21 RXD2 PB22 RTS2 PB23 CTS2 PB24 SCK2 PB25 RTS0 PB26 CTS0 PB27 NCS3 PB28 TCK/SWCLK PB29 TDI PB30 TDO/TRACESWO PB31 TMS/SWDIO Notes: 1. SAM3X only 2. SAM3A only SAM3X/A SAM3X Peripheral B Extra Function (2) TIOA3 (2) TIOB3 (2) TIOA4 (2) TIOB4 (2) TIOA5 (2) TIOB5 (2) PWML4 (2) PWML5 (2) ...
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PIO Controller C Multiplexing Table 11-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 PC1 PC2 D0 PC3 D1 PC4 D2 PC5 D3 PC6 D4 PC7 D5 PC8 D6 PC9 D7 PC10 D8 PC11 D9 PC12 ...
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PIO Controller D Multiplexing Table 11-5. Multiplexing on PIO Controller D (PIOD) I/O Line Peripheral A PD0 A10 PD1 A11 PD2 A12 PD3 A13 PD4 A14 PD5 A15 PD6 A16 PD7 A17 PD8 A21/NANDALE PD9 A22/NANDCLE PD10 NWR1/NBS1 PD11 ...
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PIO Controller E Multiplexing Table 11-6. Multiplexing on PIO Controller E (PIOE) I/O Line Peripheral A PE0 A19 PE1 A20 PE2 A21/NANDALE PE3 A22/NANDCLE PE4 A23 PE5 NCS4 PE6 NCS5 PE7 PE8 PE9 TIOA3 PE10 TIOB3 PE11 TIOA4 PE12 ...
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PIO Controller F Multiplexing Table 11-7. Multiplexing on PIO Controller F (PIOF) I/O Line Peripheral A PF0 SPI1_NPCS1 PF1 SPI1_NPCS2 PF2 SPI1_NPCS3 PF3 PWMH3 PF4 CTS3 PF5 RTS3 SAM3X/A SAM3X Peripheral B Extra Function Comments 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 ...
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Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...
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Support for two PDC channels with connection to receiver and transmitter – Connection to Peripheral DMA Controller or DMA Controller (TWI0) Channel 12.4 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications ...
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Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Interfaced with Peripheral DMA (PDC) Channels to Reduce Processor Overhead (All USARTs) and with the DMA Controller (DMAC) (USART0 and 1) 12.5 Serial ...
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... Pulse Width Modulation Controller (PWM) • One Eight-channel (SAM3A and 144-pin SAM3X) or One Four-channel (100-pin SAM3X) 16- bit PWM Controller, 16-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs – ...
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Each Slot for either a High Speed MultiMediaCard Bus ( Cards • Support for Stream, Block and Multi-block Data Read and Write • Supports Connection to DMA Controller (DMAC) – Minimizes Processor Intervention for ...
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Automatic Window Comparison of Converted Values • Write Protect Registers 12.11 Digital-to-Analog Converter (DAC) • 2 channels, 12-bit DAC • mega-sample conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources for ...
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FIFO and 128-byte receive FIFO • Automatic pad and CRC generation on transmitted frames • Automatic discard of frames received with errors • Address checking logic supports up to four specific 48-bit addresses • Support Promiscuous Mode ...
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Package Drawings The SAM3X/A series devices are available in QFP (LQFP or PQFP) and LFBGA packages. Figure 13-1. 100-lead LQFP Package Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional ...
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Figure 13-2. 100-ball LFBGA Package Drawing 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 SAM3X/A SAM3X ...
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Figure 13-3. 144-lead LQFP Package Drawing SAM3X/A SAM3X 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 ...
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Figure 13-4. 144-ball LFBGA Package Drawing All dimensions are in mm 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 SAM3X/A SAM3X ...
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Marking All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats: where • “YY”: manufactory year • “WW”: manufactory week • “V”: revision “XXXXXXXXX”: lot number SAM3X/A ...
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... Ordering Information Table 14-1. SAM3X/A Ordering Information Ordering Code MRL ATSAM3A4CA-AU A ATSAM3A8CA-AU A ATSAM3A4CA-CU A ATSAM3A8CA-CU A ATSAM3X4CA-AU A ATSAM3X8CA-AU A ATSAM3X4CA-CU A ATSAM3X8CA-CU A ATSAM3X4EA-AU A ATSAM3X8EA-AU A ATSAM3X4EA-CU A ATSAM3X8EA-CU A 11057BS–ATARM–13-Jul-12 11057BS–ATARM–13-Jul-12 Flash (Kbytes) Package 256 LQFP100 512 LQFP100 256 LFBGA100 512 LFBGA100 256 ...
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Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the review and approval loop. Doc. Rev 11057BS Comments SDRAM Controller info removed: “Signal Description List”; Table 11.1, “Peripheral ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or ...