SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet
SC16C2550B_07
Related parts for SC16C2550B_07
SC16C2550B_07 Summary of contents
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SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 04 — 15 February 2007 1. General description The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial ...
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NXP Semiconductors N Baud generation ( Mbit/s) I False start-bit detection I Complete status reporting capabilities I 3-state output TTL drive capabilities for bidirectional data bus and control bus I Line break generation and detection I Internal diagnostic ...
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NXP Semiconductors 4. Block diagram SC16C2550B DATA BUS IOR IOW CONTROL RESET REGISTER CSA SELECT CSB INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C2550B SC16C2550B_4 Product data sheet ...
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NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for HVQFN32 Fig 3. Pin configuration for DIP40 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs terminal 1 ...
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NXP Semiconductors Fig 4. Pin configuration for PLCC44 Fig 5. Pin configuration for LQFP48 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin HVQFN32 DIP40 PLCC44 LQFP48 CSA CSB ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin HVQFN32 DIP40 PLCC44 LQFP48 RESET RXRDYA - - 34 RXRDYB - - 23 TXRDYA - - 1 TXRDYB - - XTAL1 10 ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin HVQFN32 DIP40 PLCC44 LQFP48 DSRA - 37 41 DSRB - 22 25 DTRA - 33 37 DTRB - 34 38 RIA - 39 43 RIB - 23 26 RTSA 23 32 ...
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NXP Semiconductors 6. Functional description The SC16C2550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is ...
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NXP Semiconductors Table 4. Chip Select CSA, CSB = 1 CSA = 0 CSB = 0 6.2 Internal registers The SC16C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the ...
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NXP Semiconductors 6.3 FIFO operation The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit trigger level. ...
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NXP Semiconductors 6.5 Programmable baud rate generator The SC16C2550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s ...
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NXP Semiconductors Table 7. Output baud rate (bit/ 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k 6.6 DMA operation The SC16C2550B FIFO trigger level provides additional flexibility to ...
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NXP Semiconductors converts the serial data back into parallel data that is then made available at the user data interface D0 through D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of ...
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NXP Semiconductors 7. Register descriptions Table 8 assigned bit functions are more fully defined in Table 8. SC16C2550B internal registers Register Default [2] General register set RHR THR XX 0 ...
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NXP Semiconductors prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. After 7 should be shifted to the center of the start bit. ...
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NXP Semiconductors 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive ...
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NXP Semiconductors regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the FIFO reaches the trigger level and transitions HIGH when the FIFO empties. 7.3.2 FIFO mode Table 10. Bit ...
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NXP Semiconductors Table 10. Bit 1 0 Table 11. FCR[ 7.4 Interrupt Status Register (ISR) The SC16C2550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user ...
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NXP Semiconductors Table 13. Bit 7:6 5:4 3:1 0 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits and the parity are selected ...
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NXP Semiconductors Table 16. LCR[ Table 17. LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 18. Bit 7 ...
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NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2550B and the CPU. Table 19. Bit SC16C2550B_4 Product data sheet 5 V, 3.3 V and ...
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NXP Semiconductors Table 19. Bit 0 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem or other peripheral device to which the SC16C2550B is connected. Four bits of this register ...
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NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C2550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C2550B external reset condition Table 21. Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 22. ...
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NXP Semiconductors 8. Limiting values Table 23. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V voltage on any other pin n T operating temperature amb T storage temperature stg ...
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NXP Semiconductors 10. Dynamic characteristics Table 25. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f oscillator/clock frequency XTAL t address set-up time ...
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NXP Semiconductors Table 25. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t delay from start to reset 28d TXRDY t RESET pulse width RESET N baud rate divisor [1] Applies to external ...
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NXP Semiconductors CSx IOR Fig 9. General read timing active IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 10. Modem input/output timing SC16C2550B_4 Product data sheet 5 ...
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NXP Semiconductors EXTERNAL CLOCK ------- XTAL t w3 Fig 11. External clock timing RX INT IOR Fig 12. Receive timing SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with ...
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NXP Semiconductors RX RXRDY IOR Fig 13. Receive ready timing in non-FIFO mode RX RXRDY IOR Fig 14. Receive ready timing in FIFO mode SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), ...
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NXP Semiconductors TX INT active IOW Fig 15. Transmit timing TX active IOW byte #1 TXRDY Fig 16. Transmit ready timing in non-FIFO mode SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, ...
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NXP Semiconductors TX IOW active byte #16 TXRDY Fig 17. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte ...
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NXP Semiconductors 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT A ...
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NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm ...
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NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT ...
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NXP Semiconductors DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.7 0.51 ...
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NXP Semiconductors 12. Soldering 12.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. ...
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NXP Semiconductors Table 26. Package thickness (mm) < 2.5 2.5 Table 27. Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that ...
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NXP Semiconductors To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward ...
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NXP Semiconductors Table 28. Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Package Surface mount BGA, HTSSON..T LFBGA, SQFP, SSOP..T VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] ...
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NXP Semiconductors 13. Abbreviations Table 29. Acronym CPU DLL DLM DMA FIFO ISDN LSB MSB RHR THR UART 14. Revision history Table 30. Revision history Document ID Release date SC16C2550B_4 20070215 • Modifications: The format of this data sheet has ...
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NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...