AD7111A Analog Devices, AD7111A Datasheet - Page 5

• Manufacturer Part Number: AD7111A
• Description: LC2MOS LOGDAC Logarithmic D/A Converter
• Manufacturer: Analog Devices

D3-D0
D7-D4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
REV. 0
CIRCUIT DESCRIPTION
GENERAL CIRCUIT DESCRIPTION
The AD7111/AD7111A consists of a 17-bit R-2R CMOS mul-
tiplying D/A converter with extensive digital logic. The logic
translates the 8-bit binary input into a 17-bit word which is
used to drive the D/A converter. Input data on the D7-D0 bus
is loaded into the input data latches using CS and WR control
signals. When using the AD7111, the rising edge of WR latches
the input data and initiates the internal data transfer to the de-
coder. A minimum time t
the data to propagate through the decoder before a new data
write is attempted.
In contrast, the AD7111A WR input is level triggered to allow
transparent operation of the latches if required.
The transfer function for the circuit of Figure 1 is given by:
0000
0.0
6.0
12.0
18.0
24.0
30.0
36.0
42.0
48.0
54.0
60.0
66.0
72.0
78.0
84.0
MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE
0001
0.375
6.375
12.375 12.75
18.375 18.75
24.375 24.75
30.375 30.75
36.375 36.75
42.375 42.75
48.375 48.75
54.375 54.75
60.375 60.75
66.375 66.75
72.375 72.75
78.375 78.75
84.375 84.75
Write Cycle Timing Diagram
V
O
or
= –V
V
0010
0.75
6.75
V
O
IN
RFSH
IN
10 exp –
, the refresh time, is required for
dB = –0.375 N
0011
1.125
7.125
13.125 13.5
19.125 19.5
25.125 25.5
31.125 31.5
37.125 37.5
43.125 43.5
49.125 49.5
55.125 55.5
61.125 61.5
67.125 67.5
73.125 73.5
79.125 79.5
85.125 85.5
0. 375 N
0100
1.5
7.5
20
Table I. Ideal Attenuation in dB vs. Input Code
0101
1.875
7.875
13.875 14.25
19.875 20.25
25.875 26.25
31.875 32.25
37.875 38.25
43.875 44.25
49.875 50.25
55.875 56.25
61.875 62.25
67.875 68.25
73.875 74.25
79.875 80.25
85.875 86.25
0110
2.25
8.25
0111
2.625
8.625
14.625 15.0
20.625 21.0
26.625 27.0
32.625 33.0
38.625 39.0
44.625 45.0
50.625 51.0
56.625 57.0
62.625 63.0
68.625 69.0
74.625 75.0
80.625 81.0
86.625 87.0
–5–
where 0.375 is the step size (resolution) in dB and N is the in-
put code in decimal for values 0 to 239. For 240 N
output is zero. Table I gives the output attenuation relative to
0 dB for all possible input codes.
The graphs on the last page give a pictorial representation of the
specified accuracy and monotonic ranges for all grades of the
AD7111/AD7111A. High attenuation levels are specified with
less accuracy than low attenuation levels. The range of mono-
tonic behavior depends upon the attenuation step size used.
1000
3.0
9.0
1001
3.375
9.375
15.375 15.75
21.375 21.75
27.375 27.75
33.375 33.75
39.375 39.75
45.375 45.75
51.375 51.75
57.375 57.75
63.375 63.75
69.375 69.75
75.375 75.75
81.375 81.75
87.375 87.75
Figure 1. Typical Circuit Configuration
DIP/SOIC
1010
3.75
9.75
PIN CONFIGURATIONS
1011
4.125
10.125 10.5
16.125 16.5
22.125 22.5
28.125 28.5
34.125 34.5
40.125 40.5
46.125 46.5
52.125 52.5
58.125 58.5
64.125 64.5
70.125 70.5
76.125 76.5
82.125 82.5
88.125 88.5
1100
4.5
AD7111/AD7111A
1101
4.875
10.875 11.25
16.875 17.25
22.875 23.25
28.875 29.25
34.875 35.25
40.875 41.25
46.875 47.25
52.875 53.25
58.875 59.25
64.875 65.25
70.875 71.25
76.875 77.25
82.875 83.25
88.875 89.25
LCCC
1110
5.25
1111
5.625
11.625
17.625
23.625
29.625
35.625
41.625
47.625
53.625
59.625
65.625
71.625
77.625
83.625
89.625
255 the