MK2771-12S Integrated Circuit Systems, MK2771-12S Datasheet - Page 3

• Manufacturer Part Number: MK2771-12S
• Description: VCXO and Set-Top Clock Source
• Manufacturer: Integrated Circuit Systems

MDS 2771-12 A
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•[phone]tel•[phone]fax
External Components
The MK2771-12 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND, and betweeen AVDD and GND,
as close to the MK2771-12 as possible. A series termination resistor of 33
output.The 13.5 MHz crystal must be connected as close to the chip as possible. The 13.5 MHz crystal
should be a parallel mode, pullable, with load capacitance of 16 pF. Consult MicroClock for recommended
suppliers. Only the crystal should be connected to X1 and X2; do not connect load capacitors to these pins.
Electrical Specifications
Notes:
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless noted)
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH (except PCS1)
Input Low Voltage, VIL (except PCS1)
Input High Voltage, VIH, PCS1 only
Input Low Voltage, VIL, PCS1 only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
AC CHARACTERISTICS (VDD = 5.0V unless noted)
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter, short term
Skew of 27 MHz outputs
27 MHz output pullability, note 3
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
2. With PCLK at 50 MHz.
3. With a pullable crystal that conforms to ICS’ specifications.
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
I C R O
C
LOC K
Conditions
Referenced to GND
Referenced to GND
Max of 10 seconds
IOH=-25mA
IOL=25mA
IOH=-8mA
No Load, note 2
Each output
All clocks
0.8 to 2.0V
2.0 to 0.8V
At 1.4V
Rising edges at 1.4V
0V
VIN
3
3V
VCXO and Set-Top Clock Source
Minimum
VDD-0.5
VDD-0.4
4.75
-500
-0.5
-65
3.5
2.4
40
0
2
0
Revision 061699
may be used for each clock
13.50000
Typical
±100
±100
200
2.5
2.5
60
7
0
Maximum
VDD+0.5
MK2771-12
5.25
260
150
500
1.5
0.8
0.5
0.4
1.5
1.5
70
60
7
0
3
Printed 11/16/00
Units
MHz
ppm
ppm
mA
mA
°C
°C
°C
pF
%
V
V
V
V
V
V
V
V
V
V
V
V
V
ns
ns
ps
ps