MM74HC597M Fairchild, MM74HC597M Datasheet

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MM74HC597M

Manufacturer Part Number
MM74HC597M
Description
8-Bit Shift Registers with Input Latches
Manufacturer
Fairchild
Datasheet

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Part Number
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Part Number:
MM74HC597MX
Manufacturer:
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Quantity:
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© 2000 Fairchild Semiconductor Corporation
MM74HC597M
MM74HC597SJ
MM74HC597N
MM74HC597
8-Bit Shift Registers with Input Latches
General Description
This high speed register utilizes advanced silicon-gate
CMOS technology. It has the high noise immunity and low
power consumption of standard CMOS integrated circuits,
as well as the ability to drive 10 LS-TTL loads.
The MM74HC597 comes in a 16-pin package and consists
of an 8-bit storage latch feeding a parallel-in, serial-out
8-bit shift register. Both the storage register and shift regis-
ter have positive-edge triggered clocks. the shift register
also has direct load (from storage) and clear inputs.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
CC
Package Number
and ground.
Top View
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS005343
Features
Truth Table
RCK SCK SLOAD SCLR
clock
edge
No
8-bit parallel storage register inputs
Wide operating voltage range: 2V–6V
Shift register has direct overriding load and clear
Guaranteed shift frequency: DC to 30 MHz
Low quiescent current: 80 A maximum
X
X
X
Package Description
X
X
X
X
X
H
H
X
L
L
L
H
H
H
X
L
L
Data Loaded to input latches
Data loaded from inputs to
shift register
Data transferred from
input latches to shift
register
Invalid logic, state of
shift register indeterminate
when signals removed
Shift register cleared
Shift register clocked
Q
January 1988
Revised August 2000
n
Q
n
www.fairchildsemi.com
1, Q
Function
0
SER

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MM74HC597M Summary of contents

Page 1

... V and ground. CC Ordering Code: Order Number Package Number MM74HC597M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC597SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC597N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0 ...

Page 2

... Functional Block Diagram Timing Diagram www.fairchildsemi.com (Positive Logic) 2 ...

Page 3

... The worst case leakage cur specification (30 will be implemented no later than Q1, CY'89 Min Max Units 1000 ns 500 ns 400 125 C A Units Guaranteed Limits 1.5 1.5 3.15 3.15 V 4.2 4.2 0.5 0.5 1.35 1.35 V 1.8 1.8 1.9 1.9 V 4.4 4.4 5.9 5.9 3.84 3.7 V 5.34 5.2 0.1 0.1 V 0.1 0.1 0.1 0.1 0.33 0.4 V 0.33 0.4 1.0 1 160 A www.fairchildsemi.com ...

Page 4

... Maximum Propagatin PHL Delay from SCLR Minimum Removal Time REM SCLR to SCK t Minimum Setup Time S from RCK to SCK t Minimum Setup Time S from SER to SCK www.fairchildsemi.com Conditions SLOAD logic “0” V 2.0–6.0V pF ...

Page 5

... and the no load dynamic current consumption 125 C A Units 150 120 1000 500 ns 400 110 110 www.fairchildsemi.com ...

Page 6

... Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow www.fairchildsemi.com Package Number M16A 6 ...

Page 7

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com ...

Page 8

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...

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