74LVC1G07 Philips Semiconductors, 74LVC1G07 Datasheet - Page 2

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74LVC1G07

Manufacturer Part Number
74LVC1G07
Description
Buffer with open-drain output
Manufacturer
Philips Semiconductors
Datasheet

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Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
2001 Apr 06
t
C
C
PLZ
SYMBOL
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
24 mA output drive (V
CMOS low power consumption
Latch-up performance 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
SOT353 package.
I
PD
Buffer with open-drain output
P
f
f
C
V
L = LOW voltage level;
Z = high-impedance OFF-state.
/t
i
o
D
CC
PD
= input frequency in MHz;
L
PZL
= output frequency in MHz;
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts.
PD
amb
propagation delay input A to output Y
input capacitance
power dissipation capacitance per gate
V
CC
= 25 C; t
2
I
f
= GND to V
i
CC
INPUT
+ (C
A
H
r
L
= 3.0 V)
= t
PARAMETER
L
f
V
2.5 ns.
CC
CC
2
.
f
o
) where:
2
C
V
CC
L
DESCRIPTION
The 74LVC1G07 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The input can be driven from either 3.3 or 5 V devices.
This feature allows the use of this device as translator in a
mixed 3.3 and 5 V environment.
Schmitt trigger action at the input makes the circuit tolerant
for slower input rise and fall time.
The 74LVC1G07 provides the non-inverting buffer.
The output of the device is an open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
= 50 pF; V
D
= 3.3 V; notes 1 and 2
in W).
CONDITIONS
CC
= 3.3 V
OUTPUT
Y
Z
L
2.2
5
7
TYPICAL
Product specification
74LVC1G07
ns
pF
pF
UNIT

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