AD8326 Analog Devices, AD8326 Datasheet
AD8326
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AD8326 Summary of contents
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... MCNS-DOCSIS upstream standard. An 8-bit serial word determines the desired output gain over a 53.5 dB range result- ing in gain changes of 0.75 dB/LSB. The AD8326 is offered in two models, each optimized to support the desired output power and resulting performance. ...
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... V p-p IN Max Gain Max Gain Equivalent Output = 31 dBmV Equivalent Output = 61 dBmV Transmit Enable Mode (TXEN = 1) Transmit Disable Mode (TXEN = 0) Sleep Mode = 259 mV p-p, V measured through a 1 OUT AD8326ARP Min Typ Max 259 16.6 1600 800 2 52.5 53.5 54.5 26.5 27.5 28.5 –27 –26 –25 0.7526 0.2 100 1 ...
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... All Gains, SLEEP, 65 MHz 0.19 V p-p IN Max Gain Max Gain Equivalent Output = 31 dBmV Equivalent Output = 61 dBmV Transmit Enable Mode (TXEN = 1) Transmit Disable Mode (TXEN = 0) Sleep Mode AD8326 measured through a 1:1 OUT AD8326ARE Min Typ Max Unit 206 mV p-p 16.6 dB 1600 800 2 pF 52.5 53.5 54 ...
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... AD8326 LOGIC INPUTS (TTL/CMOS Compatible Logic) Parameter Logic “1” Voltage Logic “0” Voltage = 5 V) CLK, SDATA, DATEN Logic “1” Current (V INH = 0 V) CLK, SDATA, DATEN Logic “0” Current (V INL Logic “1” Current ( TXEN INH Logic “0” Current (V ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8326 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... CC 20, 23 TXEN Transmit Enable pin. Logic 1 powers up the part. SLEEP 7 Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A Logic 0 powers down the part (High Connection to these pins. 11, 13, 16, 18, V Common Negative External Supply Voltage. A 0.1 F capacitor must decouple each pin. ...
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... S 30 67dBmV @ MAX GAIN OUT 29.0 27.5 26.0 24.5 23.0 21 – 10MHz TXEN = 1 – 12V S –34 –38 –42 –46 –50 1000 AD8326 + – 0pF 10pF 20pF 50pF L 10 100 FREQUENCY – MHz GAIN CONTROL – Decimal ...
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... AD8326 – 12V S – 42MHz P = 67dBmV @ MAX GAIN O –60 –65 –70 –75 –80 –85 – GAIN CODE – Decimal – 12V(ARP) S – 69dBmV @ MAX GAIN – 68dBmV @ MAX GAIN –65 O –70 – 67dBmV @ MAX GAIN O – 65dBmV @ MAX GAIN O – ...
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... V = 12V(ARP) S 180 160 140 120 100 –40 –30 –20 –10 AD8326 CH PWR +10.41dBm ACP UP –58.83dB ACP LOW –59.06dB 100kHz/ SPAN 1MHz SLEEP 10 100 1000 FREQUENCY – MHz TRANSMIT ENABLE TRANSMIT DISABLE ...
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... Most Significant Bit (MSB) first, on the rising edge of the CLK pulses. Since a 7-bit shift register is used in the AD8326, the MSB of the 8-bit word is a “don’t care” bit and is shifted out of the register on the eighth clock pulse ...
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... IN system, and a Differential Signal Source The AD8326 evaluation board is also capable of accepting a differential input signal. This requires the installation of a 165 resistor in R12, the removal of R13–R14, R17–R18, and the installation of 0 results in a differential input impedance of 150 . Other differ- ...
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... The –5 V supply should also be delivered to each of the V pins with a low impedance bus. The power buses EE should be decoupled to ground with tantalum capacitor located close to the AD8326ARE. In addition to the 10 F capaci- tor, all and BYP pins should be individually decoupled ground with 0 ...
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... It should be noted that the AD8326 was characterized with the TOKO 617DB-A0070 transformer. TPC 7, TPC 8, TPC 13, and TPC 14 show the AD8326 second and third harmonic distortion performance versus fundamental frequency for various output power levels. These figures are useful for determining the in band harmonic levels from 5 MHz to 65 MHz ...
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... Transmit Enable and Sleep Mode The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8326 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmis- sion while maintaining a 75 back termination ...
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... AD8326 AD8326 Evaluation Board Rev. B – Revised - November 22, 2000 Qty. Description Size Tantalum Chip Capacitor 4 0 1206 Size Ceramic Chip Capacitor 14 0 603 Size Ceramic Chip Capacitor 9 0 1/8 W. 1206 Size Chip Resistor 1 78.7 1% 1/8 W. 1206 Size Chip Resistor ...
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... MAX 0.0118 (0.30) 0.006 (0.15) 0.0256 SEATING (0.65) 0.0075 (0.19) 0.000 (0.00) PLANE BSC CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm) 0.410 (10.41) 0.400 (10.16) 0.016 (0.41) 45° 0.010 (0.25 0.040 (1.27) 0.0125 (0.32) 0.024 (0.61) 0.0091 (0.23) 0.177 (4.50) 0.252 0.173 (4.40) (6.40) BSC 0.169 (4.30 0.030 (0.75) 0.0079 (0.20) 0.024 (0.60) 0.0035 (0.09) 0.177 (0.45) AD8326 ...
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