SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 38

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.5.3
This section describes the operation of the register bits in the SAA7391 host interface block.
7.5.3.1
This is a 12-byte FIFO used to transfer data from the microcontroller to the host. To transfer data the ‘trant’ bits (0 to 2)
of the DTCTR register must be set to 101.
7.5.3.2
Table 57 IFCTRL: address FF81H (note 1)
Note
1. Bits ‘cmdien’, ‘dteien’, ‘drqien’ and ‘ultra_stopien’, are the enable bits for interrupt bits ‘cmdi’, ‘dtei’, ‘drqi’ and
7.5.3.3
These are the ATAPI byte count registers. DBCL is the lower byte (bits 7 to 0) register and DBCH is the higher byte
(bits 15 to 8) register. These registers are read/writable for both the PC host and microcontroller.
Table 58 ATAPI byte count registers; addresses FF82H (DBCL) and FF83H DBCH)
The data byte counter is used by the microcontroller to control the number of bytes that are transferred during a data
transfer. During memory-to-host data transfers the data byte counter is decremented after every host read. During
host-to-memory data transfers the data byte counter is decremented as data is written into the external buffer memory.
The host may write to DBCL/DBCH to indicate to the microcontroller the maximum transfer/reception length, which may
be updated by the auto sequencer PACKETSIZE STORE registers or from the TRANSFER COUNTER (for the
remainder packet size) or directly by the microcontroller. The host can then read back the updated byte count to be
transferred.
7.5.3.4
Writing to this register starts a data transfer. The data written is discarded.
7.5.3.5
Writing to this register clears the DTEI interrupt and the ‘A0comp/crc_error’ flag. The data written is discarded.
1997 Aug 01
ACCESS
ACCESS
ATAPI CD-R block encoder/decoder
‘ultra_stop’ in the IFSTAT register. These are interrupt masks, enabling/disabling the microcontroller interrupt pin.
They do not affect the bits in the IFSTAT register. If set to logic 1, the corresponding interrupt is enabled. It should
be noted that these masks do not clear the interrupts. Bit 2 (srstien) is asserted at power-on reset, enabling the ‘srsti’
interrupt. If set to logic 1 the ‘srsti’ interrupt is disabled.
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D
ESCRIPTION OF THE HOST INTERFACE REGISTERS
ADATA
IFCTRL
DBCL and DBCH
DTRG
DTACK
cmdien
BIT 7
BIT 7
dteien
BIT 6
BIT 6
drqien
BIT 5
BIT 5
Data Byte Count register bits (bits 15 to 8)
Data Byte Count register bits (bits 7 to 0)
ultra_stopien
BIT 4
BIT 4
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BIT 3
BIT 3
srstien
BIT 2
BIT 2
BIT 1
BIT 1
Objective specification
SAA7391
BIT 0
BIT 0