PALCE20V8-10DMB Cypress Semiconductor, PALCE20V8-10DMB Datasheet

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PALCE20V8-10DMB

Manufacturer Part Number
PALCE20V8-10DMB
Description
Flash Erasable/ Reprogrammable CMOS PAL Device
Manufacturer
Cypress Semiconductor
Datasheet
Cypress Semiconductor Corporation
Document #: 38-03026 Rev. **
Features
PAL is a registered trademark of Advanced Micro Devices, Inc.
• Active pull-up on data input pins
• Low power version (20V8L)
• Standard version has low power
• CMOS Flash technology for electrical erasability and
• User-programmable macrocell
Logic Block Diagram (PDIP/CDIP/QSOP)
reprogrammability
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
— 90 mA max. commercial
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
— Output polarity control
— Individually selectable for registered or combinato-
(15, 25 ns)
(15, 25 ns)
rial operation
GND
12
OE/I
13
11
11
I
10
MUX
14
I
12
10
I
9
Macrocell
8
I/O
15
0
9
I
8
Macrocell
8
I/O
16
1
I
8
7
Macrocell
3901 North First Street
I/O
8
17
PROGRAMMABLE
Reprogrammable CMOS PAL
2
AND ARRAY
I
7
(64 x 40)
6
Macrocell
I/O
8
18
3
I
6
5
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
• QSOP package available
• High reliability
Macrocell
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
— Proven Flash technology
— 100% programming and functional testing
8
I/O
19
4
I
4
5
San Jose
Macrocell
8
I/O
20
I
5
4
3
Macrocell
8
I/O
21
I
3
2
6
CA 95134
Flash Erasable,
Macrocell
I/O
Revised March 26, 1997
22
I
8
1
2
7
PALCE20V8
CLK/I
23
I
13
MUX
1
408-943-2600
0
Device
20V8–1
V
24
CC

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PALCE20V8-10DMB Summary of contents

Page 1

... The device provides inputs and 8 outputs. The PALCE20V8 can be electrically erased and re- programmed. The programmable macrocell enables the de- vice to function as a superset to the familiar 24-pin PLDs such as 20L8, 20R8, 20R6, 20R4 ...

Page 2

... Power-Up Reset All registers in the PALCE20V8 power- logic LOW for predictable system initialization. For each register, the associ- ated output pin will be HIGH due to active-LOW outputs. Document #: 38-03026 Rev. ** ...

Page 3

... Latch-Up Current..................................................... >200 +150 C Operating Range +125 C Range Commercial 0.5V to +7.0V Industrial [1] 0.5V to +7.0V Military 0.5V to +7.0V Note the “instant on” case temperature. A PALCE20V8 Devices Emulated Registered Med PALs Registered Med PALs Small PALs Small PALs 20L8 only Adjacent 1 0 Macrocell ...

Page 4

... Output Open MHz 15L, 25L ns (counter) 10, 15 15L, 25L ns Test Conditions MHz 2. MHz OUT Test Conditions Normal Programming Conditions PALCE20V8 Min. Max. Unit Com’l 2.4 V Mil/Ind Com’l 0.5 V Mil/Ind [3] 2.0 V [3] 0.5 0 100 ...

Page 5

... Document #: 38-03026 Rev. ** ALL INPUT PULSES 90% 10 OUTPUT TEST POINT 20V8–6 Commercial 200 390 5 pF PALCE20V8 90% 10 20V8–5 Military R R Measured Output Value 1 2 390 750 1.5V 1. Page 0.5V + 0.5V ...

Page 6

... LOW level has risen to 0.5 volts above V internal (1 measured (see Note 7 above) minus t MAX MAX3 PALCE20V8 20V8 10 20V8 15 20V8 25 Min. Max. Min. Max. Min ...

Page 7

... Document #: 38-03026 Rev. ** [2] 20V8 10 Min. Max [ [7] 10 [7, [ 62.5 62.5 [7,12 [7, 13] [7] 1 PALCE20V8 20V8 15 20V8 25 Min. Max. Min. Max 41 33.3 50 33.3 8 ...

Page 8

... Power-Up Reset Waveform POWER 10% SUPPLY VOLTAGE REGISTERED ACTIVE LOW OUTPUTS CLOCK Document #: 38-03026 Rev 90 MAX = PALCE20V8 [10] [10 PXZ ER EA PZX [10] [10 PXZ ER EA PZX 20V8– 20V8– ...

Page 9

... Functional Logic Diagram for PALCE20V8 PIN NUMBERS DIP (PLCC) PACKAGE 1 ( (3) 0 280 3 (4) 320 600 4 (5) 640 920 5 (6) 960 1240 6 (7) 1280 1560 7 (9) 1600 1880 8 (10) 1920 2200 9 (11) 2240 2520 10 (12) 11 (13) 2568 BYTE7 MSB LSB Document #: 38-03026 Rev ...

Page 10

... Ordering Information for PALCE20V8 (mA) (ns) (ns) (ns) Ordering Code 115 PALCE20V8 5JC 115 7 PALCE20V8 7JC PALCE20V8 7PC 115 PALCE20V8 10JC PALCE20V8 10PC PALCE20V8 10QC 130 PALCE20V8 10JI PALCE20V8 10PI PALCE20V8 10DMB PALCE20V8 10LMB 90 15 ...

Page 11

... Ordering Information for PALCE20V8L (mA) (ns) (ns) (ns) Ordering Code PALCE20V8L 15JC PALCE20V8L 15PC PALCE20V8L 15QC PALCE20V8L 15JI PALCE20V8L 15PI PALCE20V8L 15QI PALCE20V8L 15DMB PALCE20V8L 15LMB PALCE20V8L 25JC PALCE20V8L 25PC PALCE20V8L 25QC 65 25 ...

Page 12

... Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL STD 1835 D 9 Config.A Document #: 38-03026 Rev. ** 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL STD 1835 C 4 PALCE20V8 Page ...

Page 13

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead Quarter Size Outline Q13 PALCE20V8 Page ...

Page 14

... Document Title: PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL® Device Document Number: 38-03026 Issue REV. ECN NO. Date ** 106371 07/11/01 Document #: 38-03026 Rev. ** Orig. of Change SZV Change from Spec Number: 38-00367 to 38-03026 PALCE20V8 Description of Change Page ...

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