MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet
MT312C
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MT312C Summary of contents
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... SL1914 Figure 1 - System Block Diagram - SNIM5 Satellite Channel Decoder DM5651 Ordering Information MT312C/CG/GP1N The MT312 is a QPSK/BPSK 1 to 45MBaud demodulator and channel decoder for digital satellite television transmissions to the European Broadcast Union ETS 300 421 specification (ref. 1). It receives ...
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MT312 Design Manual 1 20 Figure 2 - System Block Diagram - SNIM5 PIN FUNCTION PIN 1 CVSS 21 2 CVDD 22 3 IIN[ ADDR[ ADDR[ ADDR[ ADDR[ ADDR[3] 28 ...
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Quick start overview The MT312 is a QPSK/BPSK 1 to 45MBaud demodulator and channel decoder for digital satellite television transmissions compliant to both DVB-S and DSS standards and other systems, such as LMDS, that use the same architecture. A Command ...
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MT312 Contents Contents 1 Functional Overview ............................................................................................. 10 1.1 Introduction ........................................................................................................................................ 10 1.2 Analogue-to-Digital Converter ............................................................................................................ 10 1.3 QPSK Demodulator ............................................................................................................................ 10 1.4 Forward Error Correction .................................................................................................................. 11 1.4.1.1 Viterbi Error Count Measurement ................................................................................................ 11 1.4.1.2 Viterbi Error Count Coarse ...
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DiSEqC Control ......................................................................................................29 5.1 Screen Printouts of DiSEqC™ Waveforms ........................................................................................ 29 5.2 DiSEqC Control Read/Write Registers ............................................................................................... 30 5.2.1 DiSEqC™ Mode Control. Register 22 (R/W) .............................................................................. 30 5.2.2 DiSEqC(tm) Ratio. Register 35 (R/W) ........................................................................................ 30 5.2.3 DiSEqC™ Instruction (R/W). ...
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MT312 Contents 10 Secondary Registers for Test and De-Bugging .................................................. 61 10.1 Read / Write Secondary Register Map ............................................................................................... 61 10.2 Secondary Registers for Test and De-Bugging Read/Write Registers .............................................. 63 10.2.1 AGC Initial Value. Register 40 (R/W) ......................................................................................... 63 ...
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Microprocessor Control ........................................................................................74 11.1 Primary 2-wire bus interface ............................................................................................................... 74 11.2 RADD: 2-Wire Register Address (W) ................................................................................................. 74 11.3 Primary 2-Wire Bus Interface ............................................................................................................. 74 11.4 Secondary 2-Wire Bus for Tuner Control ........................................................................................... 75 11.5 Examples of 2-Wire Bus ...
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MT312 Contents List of figures Figure 1 System Block Diagram - SNIM5 ............................................................................................. 1 Figure 2 System Block Diagram - SNIM5 ............................................................................................. 2 Figure 3 MT312 Functional Block Diagram ........................................................................................... 3 Figure 4 Viterbi block diagram ............................................................................................................11 Figure 5 Viterbi ...
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List of tables Table 1 MT312 pin-out ....................................................................................................................... 2 Table 2 MT312 register map overview ...............................................................................................18 Table 3 Viterbi code rate indication ....................................................................................................49 Table 4 Sigma Delta clock decimation ratio programming ..................................................................52 Table 5 MPEG clock modes 54 Table 6 ...
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MT312 Functional Overview PLEASE NOTE: This manual has the following convention: All numerical values are shown as decimal numbers, unless otherwise defined. 1. Functional Overview 1.1 Introduction MT312 is a single-chip variable rate digital QPSK/ BPSK satellite demodulator and channel ...
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Forward Error Correction The MT312 contains FEC blocks to enable error correction for DVB-S and DSS transmissions. The Viterbi decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. The block features automatic ...
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MT312 Functional Overview ERROR COUNT 0 0 IRQ Figure 5 - Viterbi error count measurement Figure 5 shows the bit errors rising until the maximum programmed value of VIT ERRPER[23:0] is reached, when an interrupt is generated on the IRQ ...
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The De-interleaver Block 1.4.3.1 DVB Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. This ensures the bytes are spaced out to avoid the possibility of a noise spike corrupting a group ...
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MT312 Functional Overview 1.4.4 The Reed Solomon Decoder Block DVB and DSS data are encoded using shortened versions of the Reed-Solomon code of block length 255, containing 239 message bytes and 16 check bytes, that is (255,239) with T = ...
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Figure 11 - DVB Energy dispersal conceptual diagram 1.4.6 Output Stage Transport stream can be output in a byte-parallel or bit-serial mode. The output interface consists of an 8-bit output, output clock, a packet validation level, ...
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MT312 Functional Overview High level input/output (MBaud, MHz) Low level register read/write 1.5.2 Symbol Rate and Code Rate Search Mode Where the Symbol rate and/or the Viterbi code rate are unknown, the MT312 can be programmed to search for QPSK/BPSK ...
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RF I/P Direct Conversion ZIF Tuner SL1935 Tank Figure 13 - Alternative System Block Diagram - SNIM6 1.7 DiSEqC™ Transmit and Receive Messages The MT312 has the capability to send and receive DiSEqC™ messages. Eight registers are provided to store ...
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MT312 Software Control 2 MT312 Software Control This section describes the sequences of register operations needed to acquire DVB and DSS channels with known or unknown parameters. Communication with the MT312 is via a standard 2- wire bus and the ...
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MT312 Initialisation 3.1 The Configuration Register (127) CONFIG[B7-0]: This register is for setting up the MT312. It must be loaded first before any other register. It can only be reset to the default value by the RESET pin being ...
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MT312 Initialisation 3.3 Initialisation Sequence MT312 will be in the power save mode after a hardware reset. The first command to be written must be to the CONFIGURATION register at address 127. After loading this register, wait 150µs before writing ...
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Spectral Inversion Spectral inversion of the QPSK signal can be caused by the transmitter or the receiver front-end. In the latter case, this could happen due to the way I-Q conversion is carried out or because the I and ...
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MT312 Initialisation 3.5.2 MT312 Configuration. Register 127 (R/W) NAME ADR B7 CONFIG 127 312 EN CONFIG[7:0]: This register is for setting up the MT312. It must be loaded first before any other register. It can only be reset by the ...
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System Clock Frequency. Register 34 (R/W) NAME ADR B7 SYS CLK 34 SYS CLK[7:0] = System clock frequency * 2 in MHz. The SYS CLK register must be programmed to indicate the system clock frequency to the calculation unit. ...
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MT312 Tuner Control 4 Tuner Control 4.1 Simple Channel Change Sequence If the MT312 is running, to change channel keeping the same signal conditions only necessary to change the tuner data and possibly the DiSEqC™ data. NO reset ...
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Program tuner via GPP in 'pass through mode' open port with Reg (40hex) send TUNER DATA via I2C bus (5 bytes). close port with Reg DiSEqC mode eg Horizontal with 22kHz on: Reg 22 ...
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MT312 Tuner Control Pin 45 = DATA2, this is a transparent, bi-directional connection to the primary DATA1. Pin 44 = CLK2, this is a transparent, bi-directional connection to the primary CLK1 then: GPP DIR[2:0] defines the ...
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FR OFF: Frequency Offset. Register 38 (R/W) NAME ADR B7 FR OFF 38 FR OFF[7:0] Frequency offset correction value in MHz x 32. This 2’s complement 8 bit number represents an offset from -4MHz to +3.96875MHz. Default value 0. ...
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MT312 Tuner Control 4.5.2 Frequency Error 1 and 2. Registers 111 - 115 (R) NAME ADR B7 FREQ ERR1 H 111 FREQ ERR1[23:16] Input frequency error coarse (high byte) FREQ ERR1 M 112 FREQ ERR1[15:8] Input frequency error coarse (middle ...
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DiSEqC Control 5.1 Screen Printouts of DiSEqC™ Waveforms Figure DiSEqC™ data byte interrupting a continuous 22kHz tone The timing periods of the 16ms before the data byte and 16ms afterwards to the interrupt being asserted are ...
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MT312 DiSEqC Control 5.2 DiSEqC Control Read/Write Registers 5.2.1 DiSEqC™ Mode Control. Register 22 (R/W) NAME ADR B7 DISEQC MODE 22 Reserved B7: Reserved. Must be set low. B6: HV H/V polarisation control: High = Horizontal, DISEQC[1] pin = high ...
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For this example, the DiSEqC™ frequency = For a 10MHz crystal, the tone frequency range is from 9.8kHz with DISEQC RATIO = 255 to 250kHz with DISEQC RATIO = 10. A lower value than 10 causes the tone frequency to ...
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MT312 DiSEqC Control This is the software (partial) reset for DISEQC2 module. If this is set the DISEQC2 listen (or receive) period, any listen operations will be aborted and DISEQC2 will wait until the end of the ...
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B1-0: 101 110 111 B[1-0]: MAX TONE PER Maximum Tone Period. B1- 5.3 DiSEqC Control Read Registers 5.3.1 DiSEqC™M 2 Interrupt Indicators. Register 118 (R) NAME ADR B7 DISEQC2 INT 118 Note that the most significant ...
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MT312 DiSEqC Control B1: End of message interrupt (reset on read). Bit B1 indicates a new message has been received. The end of a message is identifi silent period of about 6 ms following a byte. The end-of-message ...
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NAME ADR B7 DISEQC2 FIFO 120 Refer to preceding section for buffer overflow. The received bytes are read from this location with 2-wire bus auto-increment bit set to zero. The received bytes will be available in the order received, i.e. ...
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MT312 QPSK Demodulator 6 QPSK demodulator 6.1 QPSK Demodulator Read/Write Registers 6.1.1 Symbol Rate. Registers (R/W) NAME ADR B7 SYM RATE H 23 SEARCH SYM RATE L 24 B15: SEARCH B14: Reserved. Must be set low B14: ...
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Bit Symbol Rate Sub Range MBaud 11 SYS CLK /2 to SYS CLK/3 10 SYS CLK/3 to SYS CLK/4 9 SYS CLK/4 to SYS CLK/6 8 SYS CLK/6 to SYS CLK/8 7 SYS CLK/8 to SYS CLK/12 6 SYS CLK/12 ...
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MT312 QPSK Demodulator 6.1.2 Viterbi mode. Register 25 (R/W) NAME ADR B7 VIT MODE 25 AUT IQ B7: AUT IQ Automatic IQ phaseHigh = Search for correct IQ phase. Low = Use IQ phase setting SP. When ...
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The Viterbi decoder will search for a signal with the code rates selected by this register. If one code rate is selected, the MT312 will search for a signal with only that code rate. If the code rate is unknown ...
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MT312 QPSK Demodulator 6.1.4 Go Command. Register 27 (R/W) NAME ADR B7-1: Reserved - not used. B0: GO High = release reset state to start signal capture, automatically reset to zero. Low = no action. If this ...
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B4: High = Enable QPSK FR LOCK indication on interrupt pin. B3: High = Enable QPSK FR UNLOCK indication on interrupt pin. B2: High = Enable QPSK calculation complete indication on interrupt pin. B1: High = Enable QPSK TS MAX ...
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MT312 QPSK Demodulator B2: High = QPSK CS LOCK B1: High = QPSK CT LOCK B0: Reserved. Must be set low. 6.2 QPSK Demodulator Read Registers 6.2.1 QPSK Interrupt. Registers (R) The majority of these interrupts are ...
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B3: Reserved High = QPSK FR UNLOCK B2: High = QPSK calculation complete B1: High = QPSK TS MAX B0: High = QPSK CS MAX Reading an Interrupt register resets that register. NAME ADR B7 QPSK INT L 02 The ...
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MT312 QPSK Demodulator 6.2.2 QPSK Status. Registers (R) NAME ADR B7 QPSK STAT H 04 B7: High = QPSK SNR MSB B6: High = QPSK SNR LSB B5: High = QPSK FR LOCK B4: High = QPSK ...
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Monitor Registers. Registers 123 - 124 (R) NAME ADR B7 MONITOR H 123 MONITOR L 124 For details, see MON CTRL register (103) on page 62. MON CTRL[3: MONITOR SYM I and MONITOR L ...
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MT312 QPSK Demodulator M PLD[15:0]: Measurement of the Phase lock detector value. Reading the bytes does NOT reset the value. The remaining settings of MON CTRL[3:0] are either reserved for diagnostic purposes or not used. 46 ...
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Forward Error Correction 7.1 Forward Error Correction Read/Write Registers 7.1.1 FEC Interrupt Enable. Register 31 (R/W) When the bits of this register are set high, they enable an event to generate an interrupt on the pin 57. All interrupts ...
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MT312 Forward Error Correction B0: BER tog High = BER toggle. This bit enables the audio signal output on the STATUS pin it indicates BER during dish alignment, see 12, section 1.4.1.2. The frequency of the signal is controlled by ...
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B2: High = Viterbi BER monitor period reached B1: High = De-scrambler lock lost B0: High = De-scrambler lock Reading an Interrupt register resets that register. 7.2.2 FEC Status. Register 6 (R) NAME ADR B7 FEC STATUS 06 B7: Reserved ...
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MT312 Forward Error Correction M SNR[14:0]: These two registers provide a indication of the signal to noise ratio of the channel being received by the MT312. It should not be taken as the absolute value of the SNR. 13312 - ...
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RS_BERCNT[23:0] Viterbi BER = -------------------------------------------------- - 8.25E8 7.2.6 Reed Solomon Uncorrected block Errors. Registers (R) NAME ADR B7 RS UBC UBC[15:8] - Reed Solomon uncorrected block errors RS UBC UBC[7:0] - ...
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MT312 Automatic Gain Control 8 Automatic Gain Control 8.1 Automatic Gain Control Read/Write Registers 8.1.1 AGC Control. Register 39 (R/W) NAME ADR B7 AGC CTRL 39 Reserved B7: Reserved. Must be set low. B6: Reserved. Must be set low. B5-4: ...
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Automatic Gain Control Read Registers 8.2.1 Measured Signal Level at MT312 Input. Register 19 (R) NAME ADR B7 SIG LEVEL 19 B7-0: SIG LEVEL[11:4]: This register provides a measurement of the MT312 input signal level. It contains the 8 ...
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MT312 MPEG Packet Data Output 9 MPEG Packet Data Ouput 9.1 MPEG Clock Modes There are four MOCLK modes of operation, controlled by register bits. MANUAL MOCLK DIS SR register 96 bit 7 register 97 bit ...
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MANUAL MOCLK = 1 and DIS This is the External MPEG Clock mode of operation. The external MOCLK is input on the MICLK pin 14. The clock supplied must be a continuous clock, otherwise the data ...
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MT312 MPEG Packet Data Output 9.3 MPEG/DSS Data Output Signals 1st byte packet n MCLKIV=1 MOCLK MDO7:0 MOSTRT MOVAL ERR_IND = 0 BKERR ERR_IND = 1 BKERR Figure 23 - MT312 output data wave form diagram Figure 22 illustrates the ...
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When ERR IND is High: BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus. BKERR goes low when there is no De-scrambler lock OR on the first byte of a packet where uncorrectable bytes ...
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MT312 MPEG Packet Data Output 9.4 Data output timing The number of PLL clocks per Byte clock is Where for QPSK, 2 for BPSK R = 204/193 for DVB, 147/135 for DSS ...
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MPEG Packet Data Output Read/Write Registers 9.5.1 Output Data Control. Register 96 (R/W) NAME ADR B7 OP CTRL 96 MANUAL MOCLK B7: MANUAL Manual MOCLK mode selection, see register 97 MOCLK B6: BKERIV High = Inverted signal on BKERR ...
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MT312 MPEG Packet Data Output Note: the BKERR signal on pin 75 can be inverted by setting the BKERIV bit CTRL register 96, see page 37. B6-4: Reserved, not used. B3-0: MON CTRL[3:0] selects which pair of ...
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Secondary Registers for Test and De-Bugging 10 Secondary Registers for Test and De-Bugging 10.1 Read / Write Secondary Register Map NAME ADR B7 AGC INIT 40 AGC MAX 42 AGC MIN 43 AGC AGC LK TH ...
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MT312 Secondary Registers for Test and De-Bugging NAME ADR B7 PLD OUTLK0 72 PLD INLK3 73 Reserved PLD INLK2 74 PLD INLK1 75 PLD INLK0 76 PLD ACC TIME 77 CS PLD MPLEN[3:0] SWEEP PAR 78 SW LIM SC[1:0] STARTUP ...
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Secondary Registers for Test and De-Bugging 10.2 Secondary Registers for Test and De-Bugging Read/Write Registers 10.2.1 AGC Initial Value. Register 40 (R/W) AGC INIT (40) AGC INIT[7:0] Front End AGC initial value. 10.2.2 AGC Maximum Value. Register 42 (R/W) AGC ...
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MT312 Secondary Registers for Test and De-Bugging 10.2.8 SNR Low Threshold Value. Register 48 (R/W) SNR THS LOW (48) SNR THS SNR low threshold value. LOW[7:0] 10.2.9 SNR HIGH Threshold Value. Register 49 (R/W) SNR THS HIGH (49) SNR THS ...
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Secondary Registers for Test and De-Bugging 10.2.15 Carrier Synchronisation Sweep Rate 3. Register 55 (R/ RATE 3 (55 Carrier Synchronisation sweep rate 3. RATE 3[7:0] 10.2.16 Carrier Synchronisation Sweep Rate 4. Register 56 (R/ ...
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MT312 Secondary Registers for Test and De-Bugging 10.2.20 Carrier Synchronisation Integral Coefficients. Registers (R/W) NAME ADR B7 CS KINT H 63 Reserved CS KINT L 64 B15: Reserved B14-10: CS KI2 [4:0] B9-5: CS KI1 [4:0] B4-0: ...
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Secondary Registers for Test and De-Bugging 10.2.25 Phase Lock Detect Threshold out of lock. Registers (R/W) NAME ADR B7 PLD OUTLK3 69 PLD OUTLK2 70 PLD OUTLK3[3:0] PLD OUTLK1 71 PLD OUTLK0 72 B31-30 ...
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MT312 Secondary Registers for Test and De-Bugging 10.2.28 Sweep PAR. Register 78 (R/W) NAME ADR B7 SWEEP PAR 78 SW LIM SC [1:0] B7-6: SW LIM SC[1:0] B5- SWEEP[2:0] B2- SWEEP[2:0] 10.2.29 Start up Time. Register ...
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Secondary Registers for Test and De-Bugging 10.2.32 Loss Lock Time. Register 82 (R/W) LOSSLOCK TM (82) LOSSLOCK TM[7:0] After the FEC locks it can unlock due to a signal fade or a cycle slip. Then the QPSK allows the following ...
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MT312 Secondary Registers for Test and De-Bugging 10.2.35 Viterbi Reference Byte 0. Register 87 (R/W) VIT REF0 (87) VIT REF0[7:0] Viterbi reference byte 0. 10.2.36 Viterbi Reference Byte 1. Register 88 (R/W) VIT REF1 (88) VIT REF1[7:0] Viterbi reference byte ...
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Secondary Registers for Test and De-Bugging 10.2.43 Byte Align Set up. Register 95 (R/W) NAME ADR B7 BA SETUP 95 BA FSM[1:0] B7-6: BA FSM[1:0] B5-4: MA MV[2: B3-0: BA UNLK[3: 10.2.44 Program Synchronising Byte. ...
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MT312 Secondary Registers for Test and De-Bugging 10.2.48 QPSK State Control. Register 102 (R/W) NAME ADR B7 QPSK ST CT 102 HLD ST B7: HLD ST B6: AFC RS B5 B4: NXT FR B3: FCE ST B2-0: ...
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Secondary Registers for Test and De-Bugging 10.2.51 QPSK Test State. Register 106 (R/W) QPSK TEST ST (106) QPSK TEST ST[7:0] 10.2.52 Test Mode. Register 125 (R/W) TEST MODE (125) TEST MODE[7:0]: 10.3 Read only Secondary Register Map Writing to these ...
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MT312 Microprocessor Control 11 Microprocessor Control 11.1 Primary 2-Wire Bus Address The 2-wire bus Address is determined by applying VDD or VSS to the ADDR[7:1] pins. See 11.3 Primary 2- Wire Bus Interface. 11.2 RADD: 2-Wire Register Address (W) RADD ...
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ADDR[7] ADDR[6] VSS VSS When the MT312 is powered up, the RESET pin 49 should be maintained low for typically 250ms (minimum 100ms) after VDD has reached normal operation levels. This is to ensure that the crystal oscillator and internal ...
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MT312 Microprocessor Control 11.5 Examples of 2-Wire Bus Messages KEY: S Start condition P Stop condition A Acknowledge ITALICS MT312 output Write operation - as a slave receiver: S DEVICE W A RADD ADDRESS (n) Read operation - MT312 as ...
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Primary 2-Wire Bus Timing t BUFF DATA1 CLK1 Figure 26 - One DiSEqC™ data byte - 0x11 (hex) plus parity bit Where Start Sr = Restart, i.e. Start without stopping first Stop. ...
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MT312 Electrical Characteristics 12 Electrical Characteristics 12.1 Recommended Operating Conditions Parameter Core power supply voltage Core power supply current Power supply voltage Power supply current Input clock frequency 1 CLK1 clock frequency Ambient operating temperature Table 9 - Recommended operating ...
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Crystal Specification Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Nominal load capacitance Equivalent series resistance NOTE: The crystal frequency should be chosen to ensure that the system clock would marginally exceed the maximum symbol ...
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MT312 Electrical Characteristics 12.5 MT312 Pinout Description Pin Name 4,5,6,7,8,11,12 ADDR[7:1] Primary 2-wire bus address defining pins 14 MICLK MPEG clock input used to generate MOCLK. Enabled when both register 96 bit 7 and register 97 bit 7 are set ...
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Note 1.8V tolerant pins with thresholds related to 3.3V. Pin Name 53 CLK1 54 DATA1 2-wire serial bus data 57 IRQ Active low interrupt output. A low output on this pin indicates an event has occurred and the microprocessor should ...
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MT312 Electrical Characteristics Pin Name 53 CLK1 24 ADCFGND ADC core front end VSS. Must be connected to analogue GND. 22 PLLGND PLL VSS. Must be connected to analogue GND. 77,78,79,80,3 IIN[5:1] Test bus, all inputs must be connected to ...
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Application Diagram Application Diagram IIN5 IIN4 IIN3 IIN2 DATA2/GPP1 IIN1 CLK2/GPP0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 TESTCLK PLLVDD PLLGND PLL1 Figure ...
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MT312 Register Map 14 MT312 Register Map RADD is a virtual register with no address containing the address of the register to be accessed written immediately after the 2-wire write address. NAME ADR B7 RADD N/A IAI 14.1 ...
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NAME ADR B7 B6 DISEQC2 122 MIN PULS PER CTRL2 CONFIG 127 312 EN DSS B 14.2 Read Only Register Map Writing to these registers will have no effect NAME ADR B7 B6 QPSK INT H 00 QPSK INT M ...
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MT312 Register Map NAME ADR B7 B6 DISEQC2 STAT 119 DISEQC2 FIFO 120 MONITOR H 123 MONITOR L 124 ID 126 DISEQC2 STATUS[7:0] DISEQC2 FIFO[7:0] MONITOR[15:8] Monitor (high byte) MONITOR[7:0] Monitor (low byte) ID[7:0] Chip ...
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INDEX Numerics 312_EN ................................................................ 22 A ADCEXT ........................................................ 19, 22 AFC ..................................................................... 39 AGC .............................................................. 52, 85 AGC_SD .............................................................. 52 B BKERR ................................................................ 59 BPSK ................................................................... 19 BSO ..................................................................... 59 C CLK1 ................................................................... 74 CONFIG .................................................. 19, 22, 85 ...
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MT312 Index MCLKINV ....................................................... 56, 59 MICLK ..................................................................48 MIN_PULS ...........................................................85 MOCLK .......................................................... 48, 56 MOCLK_RATIO ........................................ 47, 48, 54 MON_CTRL .........................................................84 MONITOR ............................................................86 MOSTRT ..............................................................56 MOVAL ................................................................56 O OP_CTRL ............................................................20 P Pass-through mode ..............................................75 pass-through mode ..............................................25 Pinout ..................................................................80 PLL_FACTOR ...
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References 1. European Digital Video Broadcast Standard, ETS 300 421 December 1994. ETS Secretariat 06921 Sophia Antipolis Cedex France. 2. Digital Satellite Equipment Control (DiSEqC™) EUTELSAT European Telecommunications Satellite Organisation 70, rue Balard - 75502 PARIS Cedex 15 France. ...
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MT312 Design Manual 90 ...