PI6C39911-5J PERICOM [Pericom Semiconductor Corporation], PI6C39911-5J Datasheet
PI6C39911-5J
Related parts for PI6C39911-5J
PI6C39911-5J Summary of contents
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... High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock Description The PI6C39911 offers selectable control over system clock func- tions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, ...
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... / and Time Unit Generator (see Logic Block Diagram). NOM PI6C39911 ( ...
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... Test Mode The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the PI6C39911 to operate as explained briefly above (for testing purposes, any of the three level inputs can have a removable jumper to ground tied LOW through a 100 Ohm resistor ...
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... Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 7. Test measurement levels for the PI6C39911 are 1.5V to 1.5V. Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. ...
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... DEV 15 the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t ODCV 16. Specified with outputs loaded with 30pF for the PI6C39911 devices. Devices are terminated through 50 Ohm 2.0V measured at 0.8V. PWL 17. t and t measured between 0 ...
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... Programmable Skew Clock Buffer - SuperClock R1 3.0V 2.0V Vth =1. REF RPWL t RPWH t t ODCV ODCV t t SKEWPR SKEWPR t SKEW0 SKEW0 SKEW2 t t SKEW3,4 SKEW3,4 t SKEW1,3,4 6 3.3V High Speed LVTTL or Balanced Output TTL Input Test Waveform 1ns 1ns t SKEW2 t SKEW3,4 t SKEW2,4 PI6C39911 t JR PS8497E 09/13/02 ...
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... System Clock Figure 2 shows the SUPERCLOCK configured as a zero-skew clock buffer. In this mode the PI6C39911 can be used as the basis for a low- skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load ...
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... Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output. 8 REF FB REF FS 4F0 4Q0 4Qx 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 TEST PS8497E PI6C39911 40 MHz 20 MHz 80 MHz 09/13/02 ...
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... TEST Figure 7. Multi-Function Clock Driver 9 3.3V High Speed LVTTL or Balanced Output LOAD Z 0 110 MHz Inverted LOAD Z 0 27.5 MHz LOAD 110 MHz Z Zero Skew 0 110 MHz Skewed LOAD –2.273ns (– PI6C39911 PS8497E 09/13/02 ...
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... TEST Figure 8 shows the PI6C39911 connected in series to construct a zero skew clock distribution tree between boards. Delays of the down stream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero- ...
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... High Speed LVTTL or Balanced Output PI6C39911 PS8497E 09/13/02 ...