VSC8163QR VITESSE [Vitesse Semiconductor Corporation], VSC8163QR Datasheet
VSC8163QR
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VSC8163QR Summary of contents
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Preliminary Data Sheet VSC8163 Features • 2.488Gb/s 16:1 Multiplexer • Targeted for SONET OC-48 / SDH STM-16 Applications • Differential LVPECL Low-Speed Interface General Description The VSC8163 is a 16:1 multiplexer with integrated clock generator for use in SONET/SDH systems ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Functional Description Low-Speed Interface The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a CLK16I phase aligned ...
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Preliminary Data Sheet VSC8163 PLL locked to reference clock. Minimum 5 CLK16 cycles (32ns) RESET Holding RESET “low” for a minimum of five CLK16 cycles, then setting “high” enables FIFO operation. Holding RESET constantly “low” bypasses the FIFO for transparent ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Figure 5: AC Termination of CLK16O+/-, REFCLKO+/- VSC8163 High-Speed Data and Clock Output The high-speed data and clock output drivers consist of a differential pair designed to drive a 50 transmis- sion line. ...
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Preliminary Data Sheet VSC8163 Clock Generator An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input. The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip loop filter. The loop ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator input signal swing should be centered about this common-mode reference voltage ( V maximum allowable amplitude. For single-ended, DC-coupling operations recommended that the user pro- vides an external reference voltage. The ...
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Preliminary Data Sheet VSC8163 AC Characteristics Figure 9: Parallel Input Data and Clock Timing Waveforms CLK16I+ Parallel Data Clock Input D[0...15]+ Parallel Data Inputs CLK16O+ Parallel Data Clock Output Figure 10: Serial Data and Clock Output Phase Timing Waveforms DO+ ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Table 1: AC Characteristics Parameters Description Data setup time to the rising T DSU edge of CLK16I+ Data hold time after the T DH rising edge of CLK16 DO± rise and ...
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Preliminary Data Sheet VSC8163 Figure 11: Differential and Single-Ended Input / Output Voltage Measurement Differential swing ) is specified ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Parameters Description V Input LOW voltage (TTL Input HIGH current (TTL Input LOW current (TTL Supply voltage CC P Power dissipation D I Supply current CC Figure ...
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Preliminary Data Sheet VSC8163 Absolute Maximum Ratings Power Supply Voltage (V ).......................................................................................................... -0.5V to +3. Input Voltage (differential inputs).................................................................................... -0. Input Voltage (TTL inputs) ...................................................................................................... -0.5V to +5.5V DC Output Voltage (TTL outputs) ........................................................................................ -0.5V ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Package Pin Descriptions VCC 4 VEEP_CLK 5 VEEP_CLK 6 VEEP_CLK 7 VCC 8 CLKO CLKO- VCC 11 VCC VEE 15 ...
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Preliminary Data Sheet VSC8163 Package Pin Descriptions Table 3: Package Pin Identification Pin # Name VCC 5 VEEP_CLK 6 VEEP_CLK 7 VEEP_CLK 8 VCC 9 CLKO+ 10 CLKO- 11 VCC 12 VCC 13 ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Pin # Name REF_FREQSEL 39 VCC 40 VEE 41 FIFO_WARN 42 VEE 43 VCC 44 RESET ...
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Preliminary Data Sheet VSC8163 Pin # Name 64 VCC VCC 67 D2- 68 D2+ 69 VEE 70 D3- 71 D3+ 72 VCC 73 D4- 74 D4+ 75 VCC 76 D5- 77 D5+ 78 VEE 79 D6- 80 ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Pin # Name 98 D12+ 99 VCC 100 D13- 101 D13+ 102 VCC 103 VCC 104 NC 105 D14- 106 D14+ 107 VCC 108 D15- 109 D15+ 110 VEE 111 NC 112 NC ...
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Preliminary Data Sheet VSC8163 Package Information PIN 128 PIN 1 EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK PIN 38 10 TYP TYP. Notes: 1) Drawing is not to scale 2) All dimensions Package ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Thermal Considerations This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance ...
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Preliminary Data Sheet VSC8163 The results of this calculation are listed in Table 6: Table 6: Maximum Ambient Air Temperature without Heatsink Airflow Max Ambient Temp( None 100 lfpm 200 lfpm 400 lfpm 600 lfpm Note that ambient air temperature ...
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OC-48 16:1 SONET/SDH MUX with Clock Generator Page 20 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION Internet: www.vitesse.com Preliminary Data Sheet VSC8163 ...