MAX9205EAV MAXIM [Maxim Integrated Products], MAX9205EAV Datasheet
MAX9205EAV
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MAX9205EAV Summary of contents
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Rev 1; 11/10 General Description The MAX9205/MAX9207 serializers transform 10-bit- wide parallel LVCMOS/LVTTL data into a serial high- speed bus low-voltage differential signaling (LVDS) data stream. The serializers typically pair with deserial- izers like the MAX9206/MAX9208, which receive the ...
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Bus LVDS Serializers ABSOLUTE MAXIMUM RATINGS AVCC, DVCC to GND..........................……………-0.3V to +4.0V IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK, PWRDN to GND......................................-0. OUT+, OUT- to GND .............................................-0.3V to +4.0V Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (T = +70°C) ...
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AC ELECTRICAL CHARACTERISTICS ( +3.0V to +3.6V, R AVCC DVCC +3.3V and T = +25°C, unless otherwise noted.) (Notes 2, 4) DVCC A PARAMETER SYMBOL TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS TCLK Center Frequency f ...
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Bus LVDS Serializers AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V, R AVCC DVCC +3.3V and T = +25°C, unless otherwise noted.) (Notes 2, 4) DVCC A PARAMETER SYMBOL Deterministic Jitter (Figure 9) ...
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PIN NAME LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024 SYNC 1, SYNC patterns. ...
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Bus LVDS Serializers Initialization Mode When V is applied, the outputs are held in high CC impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. When the supply voltage reaches 2.35V, the PLL starts to lock to a ...
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Applications Information Power-Supply Bypassing Bypass AVCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to AVCC. Bypass DVCC with high-fre- quency surface-mount ceramic 0.1µF and ...
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Bus LVDS Serializers OUT+ OUT- Figure 4. Output Load and Transition Times TCLK IN_ TIMING SHOWN FOR TCLK_R/F = LOW Figure 5. Data Input Setup and Hold Times OUT± Figure 6. High-Impedance ...
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PWRDN TCLK OUT± HIGH IMPEDANCE SYNC 1 = SYNC 2 = LOW EN = HIGH TCLK_R/F = HIGH Figure 7. PLL Lock Time and PWRDN High-Impedance Delays IN IN0 - IN9 SYMBOL TCLK 1.5V OUT± TCLK_ ...
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Bus LVDS Serializers The serializers can operate in a variety of topologies. Examples of double-terminated point-to-point, mul- tidrop, point-to-point broadcast, and multipoint topolo- gies are shown in Figures 11 through 14. Use 1% surface-mount termination resistors. A point-to-point connection ...
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A point-to-point version of the multidrop bus is shown in Figure 13. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to the multidrop bus, more interconnect is traded ...
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Bus LVDS Serializers ASIC ASIC MAX9205 MAX9205 MAX9207 MAX9207 54Ω Figure 14. Multipoint Pin Configuration TOP VIEW + 1 SYNC1 2 SYNC2 3 IN0 4 IN1 MAX9205 MAX9207 5 IN2 PWRDN 6 IN3 7 IN4 8 IN5 9 IN6 ...
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REVISION REVISION NUMBER DATE 0 5/01 Initial release 1 11/10 Updated Ordering Information, Absolute Maximum Ratings, and Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent ...