MAX509-MAX510 MAXIM [Maxim Integrated Products], MAX509-MAX510 Datasheet

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MAX509-MAX510

Manufacturer Part Number
MAX509-MAX510
Description
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
The MAX509/MAX510 are quad, serial-input, 8-bit volt-
age-output digital-to-analog converters (DACs). They
operate with a single +5V supply or dual ±5V supplies.
Internal, precision buffers swing rail-to-rail. The refer-
ence input range includes both supply rails.
The MAX509 has four separate reference inputs, allow-
ing each DAC's full-scale range to be set independently.
20-pin DIP, SSOP, and SO packages are available. The
MAX510 is identical to the MAX509 except it has two ref-
erence inputs, each shared by two DACs. The MAX510
is housed in space-saving 16-pin DIP and SO packages.
The serial interface is double-buffered: A 12-bit input
shift register is followed by four 8-bit buffer registers and
four 8-bit DAC registers. A 12-bit serial word is used to
load data into each register. Both input and DAC regis-
ters can be updated independently or simultaneously
with single software commands. Two additional asyn-
chronous control pins provide simultaneous updating
(LDAC) or clearing (CLR) of input and DAC registers.
The interface is compatible with Microwire
QSPI
compatible. A buffered data output provides for read-
back or daisy-chaining of serial devices.
19-0155; Rev 2; 1/96
_______________Functional Diagrams
Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
_______________General Description
DOUT
Functional Diagrams continued at end of data sheet.
CS DIN SCLK
REGISTER
CONTROL
TM
CLR
12-BIT
SHIFT
SR
. All digital inputs and outputs are TTL/CMOS
LDAC
CONTROL
DECODE
AGND
DGND V
INPUT
REG A
INPUT
REG B
INPUT
REG C
INPUT
REG D
________________________________________________________________ Maxim Integrated Products
MAX509
SS
REG C
REG D
REG A
REG B
V
DAC
DAC
DAC
DAC
DD
REFB
REFC
DAC A
DAC C
REFA
DAC B
DAC D
REFD
TM
and SPI/
OUTD
OUTC
OUTA
OUTB
with Rail-to-Rail Outputs
Quad, Serial 8-Bit DACs
____________________________Features
Ordering Information continued on last page.
* Dice are specified at +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
_________________Pin Configurations
______________Ordering Information
MAX509ACPP
MAX509BCPP
MAX509ACWP
MAX509BCWP
MAX509ACAP
MAX509BCAP
MAX509BC/D
Single +5V or Dual ±5V Supply Operation
Output Buffer Amplifiers Swing Rail-to-Rail
Reference Input Range Includes Both Supply Rails
Calibrated Offset, Gain, and Linearity (1LSB TUE)
10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0) and Microwire
Double-Buffered Registers for Synchronous
Updating
Serial Data Output for Daisy-Chaining
Power-On Reset Clears Serial Interface and Sets
All Registers to Zero
Pin Configurations continued at end of data sheet.
TOP VIEW
PART
DGND
OUTB
OUTA
AGND
DOUT
LDAC
REFB
REFA
N.C.
V
SS
TEMP. RANGE
10
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
1
2
3
4
5
6
7
8
9
DIP/SO/SSOP
MAX509
PIN-PACKAGE
20 Plastic DIP
20 Plastic DIP
20 Wide SO
20 Wide SO
20 SSOP
20 SSOP
Dice*
20
19
18
17
16
15
14
13
12
11
OUTC
OUTD
V
REFC
REFD
CS
N.C.
DIN
SCLK
CLR
DD
(LSB)
±1
±1 1/2
±1
±1 1/2
±1
±1 1/2
±1 1/2
TUE
1

Related parts for MAX509-MAX510

MAX509-MAX510 Summary of contents

Page 1

... The MAX509 has four separate reference inputs, allow- ing each DAC's full-scale range to be set independently. 20-pin DIP, SSOP, and SO packages are available. The MAX510 is identical to the MAX509 except it has two ref- erence inputs, each shared by two DACs. The MAX510 is housed in space-saving 16-pin DIP and SO packages. ...

Page 2

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ABSOLUTE MAXIMUM RATINGS V to DGND ..............................................................-0.3V, + AGND...............................................................-0.3V, + DGND ...............................................................-6V, +0. AGND ...............................................................-6V, +0. .................................................................-0.3V, +12V DD SS ...

Page 3

... Signal-to-Noise + Distortion Ratio SINAD Multiplying Bandwidth Wideband Amplifier Noise _______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs CONDITIONS MAX509 Code = 55 hex MAX510 MAX509 Code = 00 hex MAX510 (Note 3) (Note 4) VREF = 4V, load regulation ≤ 1/4LSB VREF = -4V -5V ±10%, SS load regulation ≤ 1/4LSB VREF = V ...

Page 4

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ELECTRICAL CHARACTERISTICS (continued +5V ±10 -5.5V, V REF = 4V, AGND = DGND = 0V 10kΩ 100pF ...

Page 5

Operating Characteristics (T = +25°C, unless otherwise noted.) A OUTPUT SINK CURRENT vs OUT VREF = + GND = 0V SS ALL DIGITAL ...

Page 6

Quad, Serial 8-DACs with Rail-to-Rail Outputs ____________________________Typical Operating Characteristics (continued +25°C, unless otherwise noted.) A ZERO-CODE ERROR vs. NEGATIVE SUPPLY VOLTAGE 5 +5V DD 4.8 VREF = +4V 4.6 4.4 4.2 4.0 3.8 3.6 3.4 0 ...

Page 7

Operating Characteristics (continued +25°C, unless otherwise noted.) A CLOCK FEEDTHROUGH A = SCLK, 333kHz B = OUT_, 10mV/div TIMEBASE = 2 s/div NEGATIVE SETTLING TIME (V = AGND 100mV 1µ DIGITAL INPUT, 5V/div ...

Page 8

... Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________________________________________Pin Description PIN NAME MAX509 MAX510 1 1 OUTB DAC B Voltage Output 2 2 OUTA DAC A Voltage Output Negative Power Supply -5V ±10%. Connect to AGND for single-supply operation – REFB Reference Voltage Input for DAC B – ...

Page 9

... CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX509/MAX510's internal shift register on the rising edge of the external serial clock. SCLK can be driven at rates up to 12.5MHz. ...

Page 10

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs CS t CSS t CSH0 SCLK DIN DOUT LDAC NOTE: TIMING SPECIFICATION t IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY. CLL Figure 2. Detailed Serial Interface ...

Page 11

... Mode 1 resets the serial output DOUT to transition at SCLK's rising edge. This is the MAX509/MAX510’s default setting after the supply voltage has been applied. The command also loads all DAC registers with the con- tents of their respective input registers, and is identical to the “ ...

Page 12

... MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 4. Connections for Microwire MAX509 MAX510 THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 5. Connections for SPI ) depends DD The MAX509/MAX510 can interface with Intel's 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted ...

Page 13

... SCLK LDAC CS1 CS2 CS3 CS MAX509 LDAC MAX510 SCLK DIN Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling individual CS. ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509 MAX509 SCLK SCLK MAX510 MAX510 ...

Page 14

... Since the REF input imped- ance is code dependent, the DAC's reference sources must have a low output impedance (no more than 32Ω for the MAX509 and 16Ω for the MAX510) to maintain output linearity. The REF input capacitance is also code 14 ...

Page 15

... OUTC OUTD V DD REFC REFD Figure 9. Suggested MAX509 PC Board Layout for Minimizing Crosstalk (Bottom View) Unipolar-Output, 2-Quadrant Multiplication In unipolar operation, the output voltages and the refer- ence input(s) are the same polarity. Figures 11 and 12 show the MAX509/MAX510 unipolar configurations. Both devices can be operated from a single supply if the reference inputs are positive ...

Page 16

... AGND V BIAS SERIAL INTERFACE NOT SHOWN 14 DD Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive 2 Offset) OUTA where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be 1 offset by V BIAS OUTB more than +1V above DGND, or more than 2.5V below DGND ...

Page 17

... F R1 330k 0.1% MAX873 +2. ICL7611A Figure 14. MAX509 AGND Bias Circuit (Negative Offset) 4-Quadrant Multiplication Each DAC output may be configured for 4-quadrant multiplication using Figure 16 and 17's circuit. One op amp and two resistors are required per channel. With [2(NB/256)-1] OUT REF where NB represents the digital word in DAC register A ...

Page 18

... Figure 15. MAX510 AGND Bias Circuit (Negative Offset) REFERENCE INPUTS ( DAC A SERIAL DAC B INTERFACE NOT SHOWN DAC C DAC 0.1 F AGND OR -5V Figure 16. MAX509 Bipolar Output Circuit 18 ______________________________________________________________________________________ REFERENCE INPUTS 4 13 MAX510 DAC A R2 330k 0.1% DAC B 0.1 F DAC DAC D 0 AGND SS ...

Page 19

... DAC C DAC 0.1 F AGND OR -5V Figure 17. MAX510 Bipolar Output Circuit __Functional Diagrams (continued) CLR DGND V AGND V REFB REFA DOUT LDAC SS DD MAX509 DECODE CONTROL INPUT DAC DAC A REG A REG A 12-BIT INPUT DAC DAC B SHIFT REG B REG B REGISTER INPUT DAC DAC C ...

Page 20

... Wide SO MAX509BEWP -40°C to +85°C 20 Wide SO MAX509AEAP -40°C to +85°C 20 SSOP MAX509BEAP -40°C to +85°C 20 SSOP MAX509AMJP -55°C to +125°C 20 CERDIP** MAX509BMJP -55°C to +125°C 20 CERDIP** MAX510ACPE 0°C to +70°C 16 Plastic DIP MAX510BCPE 0°C to +70°C 16 Plastic DIP MAX510ACWE 0° ...

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