DS80E100 NSC [National Semiconductor], DS80E100 Datasheet - Page 6

• Manufacturer Part Number: DS80E100
• Description: 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables
• Manufacturer: NSC [National Semiconductor]

www.national.com
Table 1. Typical Through Response
Block Diagram
Application Information
DS80EP100 DEVICE DESCRIPTION
The DS80EP100 Power-Saver equalizer is a passive network
circuit composed of resistive, capacitive, and inductive com-
ponents (See Figure 4). A Differential bridged T-network com-
pensates for the transmission medium losses and minimizes
medium-induced deterministic jitter with FR4 and cables. The
equalizer attenuates low frequency signals and is a bandpass
filter at the resonant frequency. The response is linear and
symmetric.
I/O TERMINATIONS
The DS80EP100 I/O impedance is 100Ω differential. The
equalizer is designed for 100Ω-balanced differential signals
and is not intended for single-ended transmission.
LINEAR COMPENSATION
The unique linear compensation feature of the DS80EP100
combined with the tiny package allows maximum flexibility in
placement. The equalizer can be placed anywhere in the data
Frequency (GHz)
FIGURE 4. Simplified Block Diagram
0.1
0.5
1.5
10
1
2
3
4
5
6
7
8
9
6
DS80EP100 Attenuation Typ
path and will provide the same compensation at the receiving
circuit. (See Simplified Application Diagram)
SYMMETRIC I/O STRUCTURES
The symmetry of the passive equalization network allows bi-
directional operation. Signals receive equal compensation
regardless of the direction of data flow. (See Simplified Block
Diagram).
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS AND NO CONNECT PADS
The differential I/Os must have a controlled differential
impedance of 100Ω. It is preferable to route all differential
lines exclusively on one layer of the board. The use of vias
should be avoided if possible. If vias must be used, they
should be used sparingly and must be placed symmetrically
for each side of a given differential pair. Differential signals
should be routed away from other signals and noise sources
on the printed circuit board. Pin 2, Pin 5, and the center DAP
have to be left as no connect. Therefore, do not connect the
landing pads of these pins to the power or ground plane. See
AN-1187 for additional information on the LLP package.
-8.25
-7.64
-6.12
-4.68
-3.57
-2.22
-1.66
-1.53
-1.77
-2.28
-3.47
-3.91
(dB)
-2.8
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