MCP4018 MICROCHIP [Microchip Technology], MCP4018 Datasheet - Page 37

• Manufacturer Part Number: MCP4018
• Manufacturer: MICROCHIP [Microchip Technology]

5.3
At times it may become necessary to perform a
Software Reset Sequence to ensure the MCP4017/18/
19 device is in a correct and known I
This only resets the I
This is useful if the MCP4017/18/19 device powers up
in an incorrect state (due to excessive bus noise, etc),
or if the Master Device is reset during communication.
Figure 5-11
software reset the device.
FIGURE 5-11:
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device.In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP4017/18/19 is driving an A
on the I
command) and is driving a data bit of ‘0’ onto the I
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP4017/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I
the MCP4017/18/19), which also forces the MCP4017/
18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP4017/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP4017/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP4017/18/19 could initiate a write cycle.
© 2009 Microchip Technology Inc.
Note:
Start
bit
Note:
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
2
Software Reset Sequence
C bus, or is in output mode (from a Read
2
C bus low to acknowledge the data sent by
This technique should be supported by
any I
Serial EEPROM devices support this tech-
nique, which is documented in AN1028.
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP4017/18/19.
shows the communication sequence to
2
C compliant device. The 24xxxx I
Nine bits of ‘1’
2
C state machine.
Software Reset Sequence
Stop bit
Start bit
2
C Interface state.
S
P
2
2
C
C
The Stop bit terminates the current I
MCP4017/18/19 wait to detect the next Start condition.
This sequence does not effect any other I
which may be on the bus, as they should disregard this
as an invalid command.
5.4
The
commands. These commands are:
•
•
Write Operation
Read Operations
MCP4017/18/19
Serial Commands
MCP4017/18/19
devices
2
support
C bus activity. The
DS22147A-page 37
2
C devices
2
serial