XC95144XV-7TQ100C XILINX [Xilinx, Inc], XC95144XV-7TQ100C Datasheet
XC95144XV-7TQ100C
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XC95144XV-7TQ100C Summary of contents
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... ESD protection exceeding 2,000V Description The XC95144XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns. © 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...
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... XC95144XV High-Performance CPLD application note XAPP361, “Planning for High Speed XC9500XV Designs.” 250 200 150 100 Clock Frequency (MHz) Figure 1: Typical I vs. Frequency for XC95144XV CC 2 221 MHz 120 MHz 120 200 160 DS051_01_121501 www.xilinx.com R DS051 (v3.0) June 25, 2007 Product Specification ...
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... In-System Programming Controller Controller I/O Blocks Figure 2: XC95144XV Architecture The XC95144XV CPLD features both LVCMOS and LVTTL I/O implementations. See The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS2 standard is used in 2.5V applications. ...
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... XC95144XV High-Performance CPLD ment. The ISE software automatically groups outputs with matching IOSTANDARD settings into the same V when no location constraints are specified. The default I/O Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage for output drivers CCIO V Input voltage relative to GND ...
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... P-term S/R to output valid PAO T GCK pulse width (High or Low) WLH T P-term clock pulse width (High or Low) PLH T Asynchronous preset/reset pulse width (High or Low) APRPW DS051 (v3.0) June 25, 2007 Product Specification XC95144XV High-Performance CPLD Test Conditions I = –4 –1 –100 μ 8.0 mA ...
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... XC95144XV High-Performance CPLD V TEST R 1 Device Output R 2 Internal Timing Parameters Symbol Buffer Delays T Input buffer delay IN T GCK buffer delay GCK T GSR buffer delay GSR T GTS buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable delay EN Product Term Control Delays ...
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... D2 348 345 342 339 336 333 330 327 324 - 4 www.xilinx.com XC95144XV High-Performance CPLD Macro- BScan cell TQ100 TQ144 CS144 (1) (1) ( ...
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... XC95144XV High-Performance CPLD XC95144XV I/O Pins (Continued) Function Macro- Block cell TQ100 TQ144 ...
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... R XC95144XV Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI (1) TDO TMS V 2.5V CCINT V CCIO CCIO GND 21, 31, 44, 62, 69, 75, 84, No Connects Notes: 1. TDO voltage is controlled by V CCIO2 DS051 (v3.0) June 25, 2007 Product Specification ...
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... Device Part Marking and Ordering Combination Information Device Type Package Speed Operating Range Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC95144XV-5TQ100C 5 ns XC95144XV-5TQ144C 5 ns XC95144XV-5CS144C 5 ns XC95144XV-7TQ100C 7.5 ns XC95144XV-7TQ144C 7.5 ns XC95144XV-7CS144C 7.5 ns XC95144XV-7TQ100I 7.5 ns XC95144XV-7TQ144I 7.5 ns XC95144XV-7CS144I 7.5 ns Notes Commercial 0° to +70° Industrial ...
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... I from 6.5 to 5.9. 06/20/02 2.3 Updated I Preliminary. Added second test condition and max measurement to I Added Part Marking Information to Ordering Information. Removed -4 device. 06/25/02 2.4 Fixed Note 1 in XC95144XV Global, JTAG and Power Pins table. 01/08/03 2.5 Corrected link on first page. 06/18/03 2.6 Updated T 08/21/03 2.7 Updated Package Device Marking Pin 1 orientation. ...