AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet

AD14160KB-4

Manufacturer Part Number

AD14160KB-4

Description

Quad-SHARC DSP Multiprocessor Family

Manufacturer

AD [Analog Devices]

Datasheet

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GENERAL DESCRIPTION

The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid

Array (CBGA) puts the power of the first generation AD14060

(CQFP) DSP multiprocessor into a very high density ball grid

array package; now with additional link and serial I/O pinned

out, beyond that from the CQFP package. The core of the multi-

processor is the ADSP-21060 DSP microcomputer. The AD14x60

modules have the highest performance—density and lowest

cost— performance ratios of any in their class. They are ideal

for applications requiring higher levels of performance and/or

functionality per unit area.

The AD14160/AD14160L takes advantage of the built-in

multiprocessing features of the ADSP-21060 to achieve 480 peak

MFLOPS with a single chip type, in a single package. The on-

chip SRAM of the DSPs provides 16 Mbits of on-module

shared SRAM. The complete shared bus (48 data, 32 address)

is also brought off-module for interfacing with expansion

memory or other peripherals.

SHARC is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

PERFORMANCE FEATURES

ADSP-21060 Core Processor ( . . .

480 MFLOPS Peak, 320 MFLOPS Sustained

25 ns Instruction Rate, Single-Cycle

16 Mbit Shared SRAM (Internal to SHARCs)

4 Gigawords Addressable Off-Module Memory

Sixteen 40 Mbyte/s Link Ports (Four per SHARC)

Eight 40 Mbit/s Independent Serial Ports (Two

5 V and 3.3 V Operation

32-Bit Single Precision and 40-Bit Extended

IEEE JTAG Standard 1149.1 Test Access Port and

PACKAGING FEATURES

452-Lead Ceramic Ball Grid Array (CBGA)

1.85" (47 mm) Body Size

0.200" Max Height

0.050" Ball Pitch

29 Grams (typical)

Instruction Execution–Each of Four Processors

Precision IEEE Floating Point Data Formats, or

32-Bit Fixed Point Data Format

from Each SHARC)

On-Chip Emulation

= 0.36 C/W

AD14160L

AD14160/

CPA

SPORT 1

SPORT 0

TDI

CPA

SPORT 1

SPORT 0

TDO

2-0

The ADSP-21060 link ports are interconnected to provide

direct communication among the four SHARCs as well as high

speed off-module access. Internally, links connect the SHARC

in a ring. Externally, each SHARC has a total of 160 Mbytes/s

link port bandwidth.

Multiprocessor performance is enhanced with embedded power

and ground planes, matched impedance interconnect, and opti-

mized signal routing lengths and separation. The fully tested

and ready-to-insert multiprocessor also significantly reduces

board space.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

SHARC_D

SHARC_A

FUNCTIONAL BLOCK DIAGRAM

DSP Multiprocessor Family

SHARC BUS (

LINK 0

LINK 5

LINK 0

LINK 5

AD14160/AD14160L

World Wide Web Site: http://www.analog.com

TDO

TDI

ADDR

SBTS, HBR, HBG, REDY, BR

31-0

DATA

47-0

LINK 0

LINK 5

TDI

LINK 0

LINK 5

TDO

Quad-SHARC

3-0

RD, WR, PAGE, ADRCLK, SW, ACK,

6-1

SHARC_C

, RPBA, DMAR

SHARC_B

1.2

, DMAG

SPORT 1

SPORT 0

SPORT 1

SPORT 0

1.2

CPA

)

2-0

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