AT43USB355M-AC ATMEL [ATMEL Corporation], AT43USB355M-AC Datasheet
AT43USB355M-AC
Available stocks
Related parts for AT43USB355M-AC
AT43USB355M-AC Summary of contents
Page 1
Features ® • AVR 8-bit RISC Microcontroller with 83 ns Instruction Cycle Time • USB Hub with One Attached and Two External Ports • USB Function with Three Programmable End-points • Program Memory Data SRAM • ...
Page 2
... VCC3 54 VSS3 55 AT43USB355E-AC PD7 56 57 PD6 PD5 58 XTAL1 59 XTAL2 60 LFT 61 PD4 62 PD3 63 PD2 64 49 PF1 PF2 PF3 52 CEXT3 53 VCC3 54 VSS3 55 AT43USB355M-AC 56 PD7 PD6 57 PD5 58 XTAL1 59 XTAL2 60 LFT 61 PD4 62 PD3 63 PD2 64 32 TEST 31 RESETN 30 PA0 29 PA1 28 PA2 27 PA3 26 CEXT1 25 VCC1 24 VSS1 ...
Page 3
Pin Assignment Pin# Signal 1 PD1 2 PD0 3 DP3 4 DM3 5 DP2 6 DM2 7 DP0 8 DM0 9 CEXT2 Power Supply/Ground 10 VCC2 Power Supply/Ground 11 VSS2 Power Supply/Ground 12 PB7 13 PB6 14 PB5 15 PB4 ...
Page 4
Signal Description Name Type Power Supply/Ground CC1 Power Supply/Ground CCA Power Supply/Ground SS1 Power Supply/Ground SSA CEXT1 Power Supply/Ground CEXTA Power Supply/Ground XTAL1 Input XTAL2 Output ...
Page 5
... MISO, SPI Slave Data Out. ICP after download complete Slave Select – In the AT43USB355E, this pin enables the external serial memory. In the AT43USB355M, this pin has no function and can be left floating or connected to VCEXT. ADC Input[0:11] – 12-bit input pins for the ADC. ...
Page 6
Figure 3. AT43USB355 Enhanced RISC Architecture 12K x 16 Program Memory Instruction Register Instruction Decoder Control Lines AT43USB355 6 Program Status and Counter Control General-purpose Registers ALU 1024 x 8 SRAM 27 GPIO Lines USB Hub and ...
Page 7
... The AT43USB355 is available in 2 versions. The program memory of the AT43USB355E is an SRAM that is automatically written from an external serial EEPROM during power-on. The Overview AT43USB355M has a masked ROM program memory. The two versions are pin, function and binary compatible. The peripherals and features of the AT43USB355 microcontroller are similar to those of the AT90S8515, with the exception of the following modifications: • ...
Page 8
The AVR uses a Harvard architecture concept – with separate memories and buses for pro- gram and data. The program memory is executed with a single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the ...
Page 9
... Program Memory The AT43USB355E contains 24K bytes on-chip downloadable memory for program storage while the AT43USB355M has a masked programmable ROM. Since all instructions are 16- or 32-bit words, the program memory is organized as 12K x 16. The AT43USB355 Program Counter (PC bits wide, thus addressing the 12,288 program memory addresses. ...
Page 10
... AT43USB355E will be written or modified. The two versions of the AT43USB355 are binary compatible. A firmware written for the AT43USB355E will work unaltered on the AT43USB355M. The only functional difference between the two versions is with respect to the serial EEPROM interface pins, GPIO PF[0:3]. ...
Page 11
Figure 5. READ Timing SRAM Data Table 3 summarizes how the AT43USB355 SRAM Memory is organized. The lower 1120 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The Memory first 96 locations address ...
Page 12
Table 2. SRAM Organization AT43USB355 12 Register File R0 R1 R30 R31 I/O Registers $00 $01 $3E $3F Data Address Space $0000 $0001 $001E $001F $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $025E $045F USB Registers $1F00 $1FFE $1FFF ...
Page 13
Table 3. USB Hub and Function Registers Address $1FFD $1FFC $1FFB $1FFA $1FF9 $1FF8 $1FF7 $1FF6 $1FF5 $1FF3 $1FF2 $1FEF $1FEE $1FE7 $1FE5 $1FE4 $1FE3 $1FE2 $1FDF $1FDD $1FDC $1FDB $1FDA $1FD7 $1FD5 $1FD4 $1FD3 $1FD2 $1FCF $1FCD $1FCC $1FCB ...
Page 14
Table 3. USB Hub and Function Registers (Continued) Address $1FBA $1FB9 $1FB8 $1FB2 $1FB1 $1FB0 $1FAA $1FA9 $1FA7 $1FA5 $1FA4 $1FA3 $1FA2 AT43USB355 14 Name Function HPSTAT3 Hub Port 3 Status Register HPSTAT2 Hub Port 2 Status Register HPSTAT1 Hub ...
Page 15
Table 4. USB Hub and Function Registers Name Address Bit 7 Bit 6 GLB_STATE $1FFB – SPRSR $1FFA – – SPRSIE $1FF9 – – SPRSMSK $1FF8 – – UISR $1FF7 SOF INT EOF2 INT UIMSKR $1FF6 SOF MSK SOF2 MSK ...
Page 16
I/O Memory The I/O space definition of the AT43USB355 is shown in the following table: Table 5. I/O Memory Space I/O (SRAM) Address $3F ($5F) $3E ($5E) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $33 ...
Page 17
Table 5. I/O Memory Space (Continued) I/O (SRAM) All AT43USB355 I/O and peripherals, except for the USB hardware registers, are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the ...
Page 18
Figure 6. USB Hardware AT43USB355 18 Port 0 XCVR Hub Repeater Serial Interface Engine Port 1 Hub Function Interface Interface Unit Unit AVR Microcontroller Port 2 XCVR Port 3 XCVR Data Address Control 2603G–USB–04/06 ...
Page 19
Functional Description On-chip Power The AT43USB355 contains four on-chip power supplies that generate 3.3V with a capacity each from the 5V power input. The on-chip power supplies are intended to supply the Supply AT43USB355 internal circuit and ...
Page 20
Figure 7. Oscillator and PLL Reset and The AT43USB355 provides 20 different interrupt sources with 11 separate reset vectors, each with a separate program vector in the program memory space. Eleven of the interrupt sources Interrupt Handling share 2 interrupt ...
Page 21
The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address $000 $004 $00E $018 ; $00d start $00e $00f $010 $011 ... USB related interrupt events are routed to reset vectors 13 and 2 ...
Page 22
Figure 8. AT43USB355 Interrupt Structure USB Interrupt Flag Register SOF EOF2 FEP3 FEP2 FEP1 FEP0 RESERVED HEP0 Suspend/Resume Register FRMWUP RSM GLB SUSP BUS RESET Reset Sources The AT43USB355 has four sources of reset: • Power-on Reset – The MCU ...
Page 23
When the USB hardware is reset, the compound device is de-configured and has to be re- enumerated by the host. When the microcontroller is reset, all I/O registers are then set to their initial values, and the program starts execution ...
Page 24
External Reset An external reset is generated by a low-level on the RESETN pin. Reset pulses longer than 200 ns will generate a reset. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset ...
Page 25
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions ...
Page 26
General Interrupt Mask Register – GIMSK Bit $3B ($5B) Read/Write Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), ...
Page 27
Timer/Counter Interrupt Mask Register – TIMSK Bit $39 ($59) Read/Write Initial Value • Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 ...
Page 28
Timer/Counter Interrupt Flag Register – TIFR Bit $38 ($58) Read/Write Initial Value • Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hardware when executing the ...
Page 29
External Interrupts The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the INT0/INT1 interrupt will trigger even if the INT0/INT1 pin is configured as an output. This fea- ture provides a way of generating ...
Page 30
MCU Control Register – MCUCR Bit $35 ($55) Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits • Bit 5 – SE: Sleep Enable The SE bit must be set (1) to make the MCU enter the sleep ...
Page 31
USB Interrupt The USB interrupts are described below. Sources Table 9. USB Interrupt Sources Interrupt SOF Received EOF2 Function EP0 Interrupt Function EP1 Interrupt Function EP2 Interrupt Function EP3 Interrupt Hub EP0 Interrupt FRWUP GLB SUSP RSM BUS RESET All ...
Page 32
USB End-point An assertion or activation of one or more bits in the end-point's Control and Status Register Interrupt Sources triggers the end-point interrupts. These triggers are different for control and non-control end- points as described in the table below. ...
Page 33
USB Interrupt Mask Register – UIMSKR Bit $1FF6 Read/Write Initial Value • Bit 7 – SOF IMSK: Start of Frame Interrupt Mask When the SOF IMSK bit is set (1), the Start of Frame Interrupt is masked. • Bit 6 ...
Page 34
USB Interrupt Acknowledge Register – UIAR Bit $1FF5 Read/Write Initial Value • Bit 7 – SOF INTACK: Start of Frame Interrupt Acknowledge The microcontroller firmware writes this bit to clear the SOF INT bit. • Bit 6 ...
Page 35
USB Interrupt Enable Register – UIER Bit $1FF3 Read/Write Initial Value • Bit 7 – SOF IE: Enable Start of Frame Interrupt When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled. • Bit 6 ...
Page 36
Suspend/Resume Interrupt Enable Register – SPRSIE Bit $1FF9 Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are reserved and are always read as zeros. • Bit 3 – BUS INT EN: USB Reset Interrupt Enable When ...
Page 37
AVR Register Set Status Register and Stack Pointer Status Register – SREG $3F ($5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. ...
Page 38
Stack Pointer Register – SP Bit $3E ($5E) $3D ($5D) Read/Write Initial Value The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be ...
Page 39
Timer/Counters The AT43USB355 provides two general-purpose Timer/Counters - one 8-bit T/C and one 16- bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescal- ing timer. Both Timer/Counters can either be used as a timer with an ...
Page 40
The 8-bit Timer/Counter0 can select clock source from CK, prescaled external pin. In Timer/Counter0 addition it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). The overflow status flag is found ...
Page 41
Timer/Counter0 Control Register – TCCR0 Bit $33 ($53) Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read as zero. • Bits – CS02, CS01, CS00: ...
Page 42
Timer/Counter1 Figure 14. Timer/Counter1 Block Diagram T/C1 OVERFLOW IRQ TIMER INT. MASK REGISTER (TIMSK) 15 T/C1 INPUT CAPTURE REGISTER (ICR1) 15 TIMER/COUNTER1 (TCNT1) 15 16-BIT COMPARATOR 15 TIMER/COUNTER1 OUTPUT COMPARE REGISTER A AT43USB355 42 T/C1 COMPARE T/C1 COMPARE MATCHB ...
Page 43
The 16-bit Timer/Counter1 can select clock source from CK, prescaled external pin. Timer/Counter1 In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Registers (TCCR1A and TCCR1B). The different status flags ...
Page 44
Timer/Counter1 Control Register A – TCCR1A Bit $2F ($4F) Read/Write Initial Value • Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare ...
Page 45
Timer/Counter1 Control Register B – TCCR1B Bit $2E ($4E) Read/Write Initial Value • Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is dis- abled. ...
Page 46
Table 14. Clock 1 Prescale Select (Continued) CS12 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the 12 MHz system clock. If the external pin modes are used for Timer/Counter1, transitions ...
Page 47
Timer/Counter1 – TCNT1H and TCNT1L Bit $2D ($4D) $2C ($4C) Read/Write Initial Value This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the ...
Page 48
Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Bit $2B ($4B) $2A ($4A) Read/Write Initial Value Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL Bit $29 ($49) $28 ($48) Read/Write Initial Value The output compare registers are 16-bit read/write registers. ...
Page 49
Timer/Counter1 Input Capture Register – ICR1H and ICR1L Bit $25 ($45) $24 ($44) Read/Write Initial Value The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) ...
Page 50
Table 16. Compare1 Mode Select in PWM Mode COM1X1 Note: Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This ...
Page 51
PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the TOP value, making a ...
Page 52
Watchdog Timer Control Register – WDTCR Bit $21 ($41) Read/Write Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and will always read as zero. • Bit 4 – WDTOE: Watch Dog ...
Page 53
Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between Interface (SPI) the AT43USB355 and peripheral devices or between several AVR devices. The AT43USB355 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master ...
Page 54
The interconnection between master and slave CPUs with SPI is shown in Figure 19. The PB7(SCK) pin is the clock output in the master mode and is the clock input in the slave mode. Writing to the SPI data register ...
Page 55
SS Pin Functionality When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin configured as an output, the pin is a general output pin ...
Page 56
Figure 21. SPI Transfer Format with CPHA = 1 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO * (From Slave) SS (To Slave) Note: * Not defined, ...
Page 57
SPI Control Register – SPCR Bit $0D ($2D) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global ...
Page 58
SPI Status Register – SPSR Bit $0E ($2E) Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR ...
Page 59
Analog-to-digital Feature list: Converter • 10-bit Resolution • 4 LSB Integral Non-linearity • ±2 LSB Absolute Accuracy • 12 – 768 µs Conversion Time • kSPS at Maximum Resolution • 12 Multiplexed Input Channels • Rail-to-rail Input ...
Page 60
Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approx- imation. The minimum value represents V on the V bits in ADMUX. Any of the twelve ADC input pins ADC11 – 0 can be ...
Page 61
The successive approximation circuitry requires an input clock frequency between 15 kHz and 1 MHz to achieve maximum resolution resolution of 10 bits is required, the input clock fre- quency to the ADC must be lower than 500 ...
Page 62
Figure 25. ADC Timing Diagram, Single Conversion Figure 26. ADC Timing Diagram, Free Running Conversion Table 21. ADC Conversion Time Sample and Hold (Cycles from Start of Conversion) Condition Normal Conversion AT43USB355 62 Conversion Time (Cycles Conversion Time ...
Page 63
ADC Multiplexer Select Register – ADMUX Bit $08 ($28) Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read as zero. • Bits 3..0 – MUX3..MUX0: Analog Channel Select ...
Page 64
ADC Control and Status Register – ADCSR Bit $07 ($27) Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned ...
Page 65
Table 23. ADC Prescaler Selections ADC Data Register – ADCL and ADCH Bit $03 ($23) $24 ($44) Read/Write Initial Value When an ADC conversion is complete, the result is found in these two registers. In Free Run Mode ...
Page 66
ADC Characteristics Symbol V REF I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other ...
Page 67
Port A Data Register – PORTA Bit $1B ($3B) Read/Write Initial Value Port A Data Direction Register – DDRA Bit $1A ($3A) Read/Write Initial Value Port A Input Pins Address – PINA Bit $19 ($39) Read/Write Initial Value The Port ...
Page 68
Port B Port 8-bit bi-directional I/O port. The Port B output buffers can sink or source 2 mA. Three I/O memory address locations are allocated for the Port B, one each for the Data Regis- ter - ...
Page 69
Port B Data Register – PORTB Bit $18 ($38) Read/Write Initial Value Port B Data Direction Register – DDRB Bit $17 ($37) Read/Write Initial Value Port B Input Pins Address – PINB Bit $16 ($36) Read/Write Initial Value The Port ...
Page 70
Port D Port 8-bit bi-directional I/O port. Its output buffers can sink or source 2 mA. Three I/O memory address locations are allocated for the Port D, one each for the Data Regis- ter - PORTD, $12($32), ...
Page 71
PortD as General PDn, General I/O Pin: The DDDn bit in the DDRD register selects the direction of this pin. If Digital I/O DDDn is set (one), PDn is con-figured as an output pin. If DDDn is cleared (zero), PDn ...
Page 72
Port F In the AT43USB355 Port F[1: 3-bit bi-directional I/O. Its output buffers can sink or source 2 mA Three I/O memory address locations are allocated for the Port F, one each for the Data Register (PORTF), $06($26), ...
Page 73
PortF as General PFn, General I/O Pin: In the AT43USB355E, after firmware downloading, the DDFn bit in the Digital I/O DDRF register selects the direction of this pin. If DDFn is set (one), PFn is con-figured as an output pin. ...
Page 74
Programming The USB hardware consists of two devices, hub and function, each with their own device address and end-points. Its operation is controlled through a set of memory mapped registers. the USB Module The exact configuration of the USB device ...
Page 75
Control Transfers at The description given below is for the function control end-point, but applies to the hub control Control End-point EP0 end-point as well if the proper registers are used. The following illustration describes the three possible types of ...
Page 76
The following information describes how the AT43USB355’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control end- point. Legend: Idle State This is the default state from power-up. Setup Response State ...
Page 77
No-data Status The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero Response State length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE interrupt token from ...
Page 78
Control Read Status The Function Interface Unit receives an OUT token from the Host with a zero length DATA1 Response State packet. The FIU responds with a NAK until TX_COMPLETE is cleared. The FIU will then ACK the retried OUT ...
Page 79
Control Write Status The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero Response State length DATA1 packet, retrying until it receives an ACK back from the Host. The FIU then asserts a ...
Page 80
Interrupt/Bulk IN The firmware must first condition the end-point through the End-point Control Register, FEND- Transfers at Function P1/2/3_CNTR: End-point Set end-point direction: set EPDIR Set interrupt or bulk: EPTYPE = Enable end-point: set EPEN The Function ...
Page 81
USB Registers The following sections describe the registers of the AT43USB355’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for which ...
Page 82
Function Address The USB function contains an address register that contains the function address assigned by Register – FADDR the host. This Function Address Register must be programmed by the microcontroller once it has received a SET_ADDRESS request from the ...
Page 83
Function End-point 1..3 Control Register – FEND-P1..3_CR Bit $1FE4 $1FE3 $1FE2 Read/Write Initial Value • Bit 7 – EPEN: End-point Enable 0 = Disable end-point 1 = Enable end-point • Bit 6..4 – Reserved These bits are reserved in the ...
Page 84
Hub End-point 0 Data Register – HDR0 Function End-point 0..3 Data Register – FDR0..3 Bit $1FD7 $1FD5 $1FD4 $1FD3 $1FD2 Read/Write Initial Value This register is used to read data from or to write data to the Hub End-point 0 ...
Page 85
Hub End-point 0 Byte Count Register – HBYTE_CNT0 Function End-point 0..3 Byte Count Register – FBYTE_CNT0..3 The contents of these registers stores the number of bytes to be sent or that was received by USB Hub and Function end-points. This ...
Page 86
Hub End-point 0 Service Routine Register – HCSR0 Function End-point 0 Service Routine Register – FCSR0 Function EP0 $1FDF Function EP0 $1FDD Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB355 and will read ...
Page 87
Hub End-point 0 Control and Acknowledge Register – HCAR0 Function End-point 0 Control and Acknowledge Register – FCAR0 Bit Hub EP0 $1FA7 Function EP0 $1FDD Read/Write Initial Value • Bit 7 – DIR: Control transfer direction It is set by ...
Page 88
Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com- plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the microcontroller. • Bit ...
Page 89
Function End-point 0..3 Control and Acknowledge Register – FCAR0..3 Function EP1 $1FA4 Function EP2 $1FA3 Function EP3 $1FA2 Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB355 and will read as zero. • Bit ...
Page 90
USB Hub The hub in a USB system provides for the electrical interface between USB devices and the host. The major functions that the hub must supports are: • Connectivity • Power management • Device connect and disconnect • Bus ...
Page 91
Hub General Registers Global State Register – GLB_STATE Bit $1FFB Read/Write Initial Value • Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB355 and will read as zeros. • Bit 4 – SUSP FLG: Suspend Flag This ...
Page 92
Hub Status Register In the AT43USB355 overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, ...
Page 93
Hub Port Control Register – HPCON Bit $1FC5 Read/Write Initial Value • Bit 7 – Reserved This bits is reserved in the AT43USB355 and will read as zero. • Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are ...
Page 94
These bits define which port is being addressed for the command defined by bits [2:0]. Selective Suspend The host can selectively suspend and resume a port through the Set Port Feature and Resume (PORT_SUSPEND) and Clear Port Feature (PORT_SUSPEND). A ...
Page 95
Hub Port Status The bits in this register are used by the microcontroller firmware when reporting a port's status Register through the Port Status Field, wPortStatus. Bits 3 (POCI) and 5 (PPSTAT) are used by the USB hardware and are ...
Page 96
Set and cleared by the hardware as controlled through Port Control register. • Bit 0 – PCSTAT: Port Connect Status device on this port 1 = Device present on this port Set to 1 for Port 1. ...
Page 97
Hub Port Status Change Register – PSCR1..3 Port1 $1FB0 Port2 $1FB1 Port3 $1FB2 Read/Write Initial Value The microcontroller firmware uses the bits in this register to monitor when a port status change has occurred, which then gets reported to the ...
Page 98
Set by hardware due to babble, physical disconnect or overcurrent except for Port 1 in which case it is set by hardware at EOF2 due to hardware events. Cleared by firmware via Host request ClearPortFeature(PORT_ENABLE). • Bit 0 – PCSC: ...
Page 99
Only if all of the Power Control Bits of ports 2 and 3 are cleared should the firmware de- assert the PWRN pin. 2. Individual Power Switching – Two microcontroller GPIO pins, PWR2N and PWR3N, must be assigned for each ...
Page 100
A remote wakeup initiated at a downstream port is similar in many respects to a global resume. The ...
Page 101
Global Resume The Host resumes signaling, the hardware detects this as global resume and propagates this signaling to all downstream ports. Finally, the hardware enables the oscillator and asserts the RSM interrupt. 2. Resume signaling detected 3. Propagate signaling downstream ...
Page 102
Selective Suspend, Downstream Ports 3. Suspend or resume port per command Selective Suspend, Embedded Function Selective Resume, Embedded Function 6. Send updated port status at next IN to end-point1 AT43USB355 102 Hardware 1. Set or Clear Port Feature PORT_SUSPEND decoded ...
Page 103
Electrical Specification Absolute Stresses beyond those listed below may cause permanent damage to the device. This is a Maximum Ratings stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the ...
Page 104
Table 33. PA, PB, PD, PF Symbol V OL2 V OH2 V IL2 V IH2 RPU C Note: Table 34. Oscillator Signals: XTAL1, XTAL2 Symbol CX1 CX2 C12 Note: AC Characteristics Table 35. ...
Page 105
Figure 28. Synchronous Data Timing Table 36. USB Driver Characteristics, Full Speed Operation Symbol TR TF TRFM ZDRV Note: Figure 29. Full-speed Load 2603G–USB–04/ SSN CSS SCK ...
Page 106
Table 37. USB Driver Characteristics, Low-speed Operation Symbol TR TF TRFM Figure 30. Low-speed Downstream Port Load Table 38. USB Source Timings, Full-speed Operation Symbol Parameter (1) TDRATE Full Speed Data Rate (1) TFRAME Frame Interval TRFI Consecutive Frame Interval ...
Page 107
Figure 31. Differential Data Jitter Figure 32. Differential-to-EOP Transition Skew and EOP Width Figure 33. Receiver Jitter Tolerance 2603G–USB–04/06 T PERIOD Crossover Differential Points Data Lines Consecutive Transitions N PERIOD XJR1 Paired Transitions N*T PERIOD Crossover T PERIOD ...
Page 108
Table 39. Hub Timings, Full-speed Operation Symbol THDD2 THDJ1 THDJ2 TFSOP TFEOPD TFHESK Table 40. Hub Timings, Low-speed Operation Symbol TLHDD TLHDJ1 TLHDJ2 TLUHJ1 TLUHJ2 TSOP TLEOPD TLHESK AT43USB355 108 Parameter Condition Hub Differential Data Delay without cable Hub Diff ...
Page 109
Table 41. Hub Event Timings Symbol TDCNN TDDIS TURSM TDRST TDSPDEV TURLK TURLSEO TURPSEO TUDEOP 2603G–USB–04/06 Parameter Condition Time to detect a downstream port connect event Time to detect a disconnect event on downstream port Awake Hub Suspended Hub Time ...
Page 110
Figure 34. Hub Differential Delay, Differential Jitter and SOP Distortion Upstream End of Cable V SS Differential Data Lines Downstream Hub Delay With Cable Figure 35. Hub EOP Delay and EOP Skew Upstream End of Cable V ...
Page 111
... Ordering Information Program Memory Ordering Code SRAM AT43USB355E-AC Mask ROM AT43USB355M-AC SRAM AT43USB355E-AU Mask ROM AT43USB355M-AU 2603G–USB–04/06 Package 64 LQFP 64 LQFP 64 LQFP 64 LQFP AT43USB355 Operation Range Commercial (0°C to +70°C) Commercial (0°C to +70°C) Green, Industrial (-40°C to +85°C) Green, Industrial (-40° ...
Page 112
Packaging Information 64AA – LQFP Dimensions in Millimeters and (Inches) Controlling Dimensions: Millimeters JEDEC STANDARD MS-026 ACB PIN 1 ID 0.50(0.020) BSC 0.20(0.008) 0.09(0.003) 2325 Orchard Parkway San Jose, CA 95131 R AT43USB355 112 PIN 1 10.10(0.397) 9.90(0.389) 0˚~7˚ 0.75(0.030) ...
Page 113
Errata Sheet Errata (All Date Codes): Missed Watchdog Timer Reset Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core are generated ...
Page 114
... Bits 2..0 of “ADC Control and Status Register – ADCSR” on page 64 was modified. • Update: The disclaimer and copyright information on the last page was modified. • Additions: Added AT43USB355E-AU and AT43USB355M-AU part numbers to Ordering Information. 2603G–USB–04/06 ...
Page 115
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...