AT22V10-15 ATMEL [ATMEL Corporation], AT22V10-15 Datasheet - Page 6

• Manufacturer Part Number: AT22V10-15
• Description: High Speed UV Erasable Programmable Logic Device
• Manufacturer: ATMEL [ATMEL Corporation]

Power Up Reset
The registers in the AT22V10 and AT22V10L are designed to
reset during power up. At a point delayed slightly from V
crossing 3.8 V, all registers will be reset to the low state. The
output state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However,
due to the asynchronous nature of reset and the uncertainty of
how V
are required:
1) The V
2) After reset occurs, all input and feedback setup times must be
met before driving the clock pin high, and
3) The clock must remain stable during t
Pin Capacitance
Note:
Erasure Characteristics
The entire fuse array of an AT22V10 or AT22V10L is erased
after exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 minutes ex-
posure using 12,000 W/cm
away from the chip. Minimum erase time for lamps at other in-
1-102
Preload of Registered Outputs
The registers in the AT22V10 and AT22V10L are provided
with circuitry to allow loading of each register asynchronously
with either a high or a low. This feature will simplify testing
since any state can be forced into the registers to control test
sequencing. A V
high; a V
setting. The preload state is entered by placing an 11.5-V to
13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the
clock pin is pulsed high, the data on the I/O pins is placed into
the ten registers.
C
C
IN
OUT
PRELOAD
CLOCK
REGISTERED
OUTPUTS
CC
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
IL
CC
actually rises in the system, the following conditions
will force it low, independent of the polarity bit (C0)
rise must be monotonic,
IH
VH
level on the I/O pin will force the register
PRELOAD ENA.
OUTPUTS DIS.
AT22V10/L
2
(f = 1 MHz, T = 25°C)
intensity lamps spaced one inch
tD
PR
FORCE I/O’S
TO VIH ORVIL
.
Typ
5
6
tD
PRELOAD DATA
CLOCKED IN
(1)
CC
tD
Max
tensity ratings can be calculated from the minimum integrated
erasure dose of 15 W sec/cm
sure, an opaque label is recommended to cover the clear window
on any UV erasable PLD which will be subjected to continuous
fluorescent indoor lighting or sunlight.
Parameter
8
8
POWER
REGISTERED
OUTPUTS
CLOCK
t
Level forced on
registered output pin
during preload cycle
PR
tD
3.8 V
V
V
Description
Power-Up
Reset Time
IH
IL
OUTPUT
VOLTAGE
REMOVED
Units
pF
pF
tD
2
. To prevent unintentional era-
tPR
Min
PRELOAD
DISABLED
Conditions
V
V
Typ
600
Register state
after cycle
IN
OUT
t
High
Low
DMIN
tW
= 0 V
= 0 V
tS
1000
Max Units
= 100 ns
ns