PALCE29M16H-25 AMD [Advanced Micro Devices], PALCE29M16H-25 Datasheet
PALCE29M16H-25
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PALCE29M16H-25 Summary of contents
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... FINAL COM’L: H-25 PALCE29M16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS High-performance semicustom logic replacement; Electrically Erasable (EE) technology allows reprogrammability 16 bidirectional user-programmable I/O logic macrocells for Combinatorial/Registered/ Latched operation Output Enable controlled by a pin or product terms Varied product term distribution for increased ...
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... The PALCE29M16 is offered in the space-saving 300-mil SKINNYDIP package as well as the plastic leaded chip carrier package I/ I/ 08740G-2 PALCE29M16H-25 a power-up Reset feature. PLCC I I ...
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... Valid Combinations lists configurations planned supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE29M16H-25 (Com’l) AMD OPTIONAL PROCESSING Blank = Standard processing PROGRAMMING REVISION /4 = First Revision (Requires current ...
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... Combinatorial output is desired when the PAL device is used to replace combinatorial glue logic. Registers and Latches are used in synchronous logic applications. P0 Preset CLK/ Reset PALCE29M16H- I 08740G-4 ...
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... Preset CLK/ Reset PALCE29M16H-25 controls whether the macrocell will be combi- controls the output po- 0 determines 2 are used to control Output Enable as pin con I/ ...
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... I/CLK/LE pin positive-going edge, active-LOW LE 0 I/CLK/LE pin negative-going edge, active-HIGH LE S Output Buffer Control 7 1 Pin-Controlled Three-State Enable 0 XOR PT-Controlled Three-State Enable 1 Permanently Enabled (Output only) 0 Permanently Disabled (Input only) PALCE29M16H-25 S Storage Element 2 1 Register 0 Latch S Output Polarity 0 1 Active LOW 0 ...
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... 08740G-10 Output Combinatorial/Active Low 08740G-12 Output Combinatorial/Active High, Figure 3b. Single Feedback Macrocells PALCE29M16H-25 AMD 08740G 08740G ...
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... 08740G-16 Output Combinatorial/Active Low (For Single Feedback Only Register Latch Programmable-AND Array Input Registered/Latched Figure 3c. All Macrocells PALCE29M16H- 08740G-15 Register Feedback ...
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... CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input- clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PALCE29M16H-25 AMD 2-335 ...
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... PRODUCT TERM (5) 4 INPUT/ I/OF 1 OUTPUT MACRO (6) 5 I/O 0 INPUT/ OUTPUT MACRO (7) 6 I/O 1 INPUT/ OUTPUT MACRO 2-336 Continued on Next Page PALCE29M16H- 23(27 22(26) I/OF 7 INPUT/ OUTPUT MACRO PRESET PRODUCT TERM 21 (25) INPUT/ I/OF 6 OUTPUT MACRO 20 (24) I/O 7 INPUT/ OUTPUT MACRO ...
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... OUTPUT MACRO (12) 10 I/OF 3 INPUT/ OUTPUT MACRO PRELOAD PRODUCT TERM (13 PALCE29M16H- INPUT/ OUTPUT MACRO INPUT/ OUTPUT MACRO INPUT/ OUTPUT MACRO INPUT/ OUTPUT MACRO AMD 18 (21) I (20) I (19) ...
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... Max OUT (Note 0 Max (Note 3) OUT Outputs Open ( Max CC and I (or I and OZL IH OZH PALCE29M16H-25 (Com’ 4. 5.25 V Min Max 0.33 0.1 2.0 0.8 10 –10 10 –10 –30 –130 ...
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... Test Conditions 5 MHz OUT + t ) SOR COR CIS AND-OR Array tCIS tCIS V Output Input Register Register PALCE29M16H-25 (Com’l) AMD Typ Unit = Min Max Unit 33.3 MHz 50 MHz tCOR ...
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... SWITCHING WAVEFORMS Combinatorial Input Combinatorial Output Combinatorial Input Registered Output Registered Input Combinatorial Output Clock 2-340 VT tPD Combinatorial Output tSOR tHOR Clock VT tCOR Output Register tSIR tHIR Clock tCIR Input Register tCIS tCWH tCWL 08740G-24 Clock Width PALCE29M16H-25 VT 08740G- 08740G-22 08740G-23 ...
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... Pin Enable Width HIGH GWH t Pin Enable Width LOW GWL LE tSTL tSIL tPTD I/O I/O tSOL tPTD tPD AND-OR Array tGIS tGIS Output Input Latch Latch Input/Output Latch Specs PALCE29M16H-25 (Com’l) AMD Min Max Unit ...
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... Transparent tGOL VT VT Note 1 tSTL 08740G-28 Latched Input LE Combinatorial Output ns after LE goes into the transparent mode. If the combinatorial GOL ns after the combinatorial input changes or t PTD PALCE29M16H-25 Latched Transparent VT tGWL tGWL 08740G-27 LE Width Transparent Input VT Latch tGIS Latched Output VT Latch 08740G-29 ...
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... ARO V T 08740G-31 Pin 11 Combinatorial/ Registered/ Latched Output Pin 11 to Output Disable/Enable ARI V T 08740G-33 Combinatorial Input Combinatorial/ Registered/Latched Output Input to Output Disable/Enable PALCE29M16H-25 (Com’l) AMD Min Max Unit ...
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... Don’t Care, Any Change Permitted Does Not Apply Output 470 5 pF PALCE29M16H-25 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010 ...
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... Therefore, only dedicated input pins should be used for the Preload command. Min 0.5 250 100 Preload Mode t D Data to be Preloaded Preload Waveform PALCE29M16H-25 AMD /V for all output pins as per pro- OH Rec. Max Unit 1.0 5.0 500 700 ns 500 ...
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... I/O pins and registers). If I/O pins are used, the observe mode could cause a value change, which would cause the device to oscillate in and out of the Observe mode. Therefore, only dedicated input pins should be used for the Observe command. Min 0.5 100 Observe Mode t D Observability Waveform PALCE29M16H-25 Rec. Max Unit 1.0 5.0 s 500 ...
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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform PALCE29M16H-25 can rise to its steady state, two CC rise must be monotonic. CC Min Max 10 See Switching Characteristics 500 V ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 2-348 SKINNYDIP 200 Ifpm air 400 Ifpm air 600 Ifpm air 800 Ifpm air PALCE29M16H-25 Typ PLCC Unit 17 11 C/W 63 ...