AIC1571 AIC [Analog Intergrations Corporation], AIC1571 Datasheet - Page 14

• Manufacturer Part Number: AIC1571
• Description: 5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers
• Manufacturer: AIC [Analog Intergrations Corporation]

PWM Output Capacitors
The load transient for the microprocessor core
requires high quality capacitors to supply the
high slew rate (di/dt) current demand.
The ESR (equivalent series resistance) and
ESL (equivalent series inductance) parameters
rather than actual capacitance determine the
buck capacitor values. For a given transient
load magnitude, the output voltage transient
change due to the output capacitor can be note
by the following equation:
After the initial transient, the ESL dependent
term drops off. Because the strong relationship
between output capacitor ESR and output load
transient, the output capacitor is usually chosen
for ESR, not for capacitance value. A capacitor
with suitable ESR will usually have a larger ca-
pacitance value than is needed for energy stor-
age.
Output Inductor Selection
Inductor value and type should be chosen
based on output slew rate requirement, output
ripple requirement and expected peak current.
Inductor value is primarily controlled by the re-
quired current response time. The AIC1571 will
provide either 0% or 100% duty cycle in re-
sponse to a load transient. The response time
to a transient is different for the application of
load and remove of load.
Where
In a typical 5V input, 2V output application, a
3µH inductor has a 1A/µS rise time, resulting in
a 5µS delay in responding to a 5A load current
step. To optimize performance, different com-
binations of input and output voltage and ex-
pected loads may require different inductor
value. A smaller value of inductor will improve
the transient response at the expense of in-
crease output ripple voltage and inductor core
saturation rating.
A common way to lower ESR and raise ripple
current capability is to parallel several capaci-
tors. In most case, multiple electrolytic capaci-
tors of small case size are better than a single
large case capacitor.
∆
∆I
t
RISE
V
OUT
OUT
=
is transient load current step.
=
V
∆I
L
IN
ESR
OUT
×
−
∆
V
I
OUT
is transient load current step.
OUT
×
∆
I
,
OUT
t
FALL
+
ESL
=
L
×
× ∆
V
∆
OUT
∆
I
OUT
I
T
OUT
, where
.
Peak current in the inductor will be equal to the
maximum output load current plus half of in-
ductor ripple current. The ripple current is ap-
proximately equal to:
The inductor must be able to withstand peak
current without saturation, and the copper re-
sistance in the winding should be kept as low
as possible to minimize resistive power loss
Input Capacitor Selection
Most of the input supply current is supplied by
the input bypass capacitor, the resulting RMS
current flow in the input capacitor will heat it up.
Use a mix of input bulk capacitors to control the
voltage overshoot across the upper MOSFET.
The ceramic capacitance for the high frequency
decoupling should be placed very close to the
upper MOSFET to suppress the voltage in-
duced in the parasitic circuit impedance. The
buck capacitors to supply the RMS current is
approximate equal to:
The capacitor voltage rating should be at least
1.25 times greater than the maximum input
voltage.
PWM MOSFET Selection
In high current PWM application, the MOSFET
power dissipation, package type and heatsink
are the dominant design factors. The conduc-
tion loss is the only component of power dissi-
pation for the lower MOSFET, since it turns on
into near zero voltage. The upper MOSFET has
conduction loss and switching loss. The gate
charge losses are proportional to the switching
frequency and are dissipated by the AIC1571.
However, the gate charge increases the
switching interval, t
MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction
temperature at high ambient temperature by
calculating the temperature rise according to
package thermal resistance specifications.
I
RMS
f = AIC1571 oscillator frequency.
I
RIPPLE
=
(1 D)
−
, where
=
(V
×
IN
D
f
−
D
SW
× ×
×
V
=
L V
OUT
which increase the upper
V
I
2
V
OUT
OUT
) V
IN
×
IN
+
OUT
12
AIC1571
1
×
;
ç
V
f L
IN
×
×
14
D
÷
2