AT83C24B-TIRIL ATMEL [ATMEL Corporation], AT83C24B-TIRIL Datasheet
AT83C24B-TIRIL
Related parts for AT83C24B-TIRIL
AT83C24B-TIRIL Summary of contents
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... Low Power Consumption – 180 mA Maximum In-rush Current – 30 µA Typical Power-down Current (without Smart Card) • MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24B) • 48MHz Clock input (for AT83C24NDS) • Industrial Temperature Range: -40 to +85°C • ...
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Acronyms TWI: Two-wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus Block Diagram DVCC EVCC RESET PRES/ INT ...
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... After reset, AT83C24 needs to be reconfigured before starting a new card session. AT83C24 QFN28 pinout EVCC 1 CMDVCC VSS QFN 28 CVSS TOP VIEW SCL 16 6 CVCC SDA 15 CVCCin AT83C24B and for AT83C24NDS /CK /RST / ...
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Table 1. Ports Description (Continued) Pad Name Pad Internal Power Supply Limits SDA VCC SCL VCC I/O EVCC C4 EVCC C8 EVCC CLK EVCC CIO CVCC CC4 CVCC CC8 CVCC CPRES VCC CCLK CVCC CRST CVCC CMDVCC EVCC VCC LI ...
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Table 1. Ports Description (Continued) Pad Name Pad Internal Power Supply CVCC CVCCin DVCC EVCC CVSS VSS Note: 4234G–SCR–01/07 ESD Pad Limits Type Description Card Supply Voltage 8 kV+ PWR CVCC is the programmable voltage output for the Card interface. ...
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Operational Modes TWI Bus Control The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds 400 Kbits per second, based on a byte-oriented ...
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Address Byte The first byte to send to the device is the address byte. The device controls if the hardware address (A2/CK, A1/RST, A0/3V pins on reset) corresponds to the address given in the address byte (A2, A1, A0 bits). ...
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Write Commands The write commands are: 1. Reset: Initializes all the logic and the TWI interface as after a power-up or power-fail reset smart card is active when RESET falls, a deactivation sequence is performed. This is a ...
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Read Command After the slave address has been configured, the read command allows to read one or several bytes in the following order: • STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1, TIMER0, CAPTURE1, CAPTURE0 • FFh is completing the transfer ...
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Card Presence Detection The card presence is provided by the CPRES pin. The polarity of card presence contact is selected with the CARDDET bit (see CONFIG1 register). A programmable filtering is controlled with the CDS[2-0] bits (see CONFIG1 ...
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CIO, CC4, CC8 Controller The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4, CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS bit value. If IODIS is reset, data are ...
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Figure 6. Clock Block Diagram with Software Activation (see page 14) Figure 7. Clock Block Diagram with Hardware Activation (see page 14) CMDVCC A1/RST CRST Controller The CRST output pin is driven by the A1/RST pin signal pin or by ...
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Figure 8. CRST Block Diagram with soft activation Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used) CMDVCC 4234G–SCR–01/07 CARDRST bit tb delay see Fig 12 CARDRST bit A1/RST CRST_SEL bit = 1 CMDVCC ART ...
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Activation Sequence Hardware Activation (DC/DC started with CMDVCC) Initial conditions: CARDDET bit must be configured in accordance to the smart card connector polarity. IT_SEL bit, CRST_SEL bit (see CONFIG4 register) must be set and CARDRST bit (see INTER- FACE register) ...
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Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1 Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1. The following sequence can be applied: 1. Card Voltage is set by software ...
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ISO 7816 constraints 200 card clock cycles Note: Timer[1-0] reset value is 400. Warm reset The AT83C24 offers a simple and accurate way to control the CRST signal during a warm reset. After an activation sequence (cold reset), ...
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Software Activation (DC/DC Started by Writing in VCARD[1:0] bits) and ART bit = 0 The activation sequence is controlled by software using TWI commands, depending on the cards to support. For ISO 7816 cards, the following sequence can be applied: ...
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Deactivation Sequence The card automatic deactivation is triggered when one the following condition occurs: • ICARDERR bit is set by hardware • VCARDERR bit is set by hardware (or by software) • INSERT is set and CARDIN is cleared (card ...
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Transparent Mode If the microcontroller outputs ISO 7816 signals, a transparent mode allows to connect RST/CLK and I/O/C4/C8 signals after an electrical level control. The AT83C24 level shifters adapt the card signals to the smart card voltage selection. The CRST ...
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Table 5. Power Modes Description Shutdown LP Mode Number Bit Bit Power Monitoring The AT83C24 needs only one power supply to run: VCC. If the ...
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Registers Table 6. CONFIG0 (Config Byte 0) Number 4234G–SCR–01/ ATRERR Bit Bit Mnemonic Description 7-6 1-0 These bits cannot be programmed and are read as 1-0. Answer to Reset Interrupt This bit is set when ...
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Table 7. CONFIG 1 (Config Byte 1) Number AT83C24 ART SHUTDOWN Bit Bit Mnemonic Description 7 X This bit should not be set. Automatic Reset Transition Set this bit to have the CRST pin changed ...
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Table 8. CONFIG2 (Config Byte 2) Number Notes: 4234G–SCR–01/ DCK2 DCK1 Bit Bit Mnemonic Description 7 X This bit should not be set. DC/DC Clock prescaler factor DCCLK is the DC/DC clock the division ...
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Table 9. CONFIG3 (Config Byte 3) Number AT83C24 EAUTO VEXT1 VEXT0 Bit Bit Mnemonic Description EVCC voltage configuration: EAUTO VEXT1 VEXT0 EVCC = 0 the regulator is switched off 1EVCC = ...
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Table 10. CONFIG4 (Config Byte Bit Number Bit Mnemonic Description 7-5 X-X-X These bits should not be set. Step Regulator mode Clear this bit to enable the automatic step-up converter (CVCC is stable even if ...
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Table 11. INTERFACE (Interface Byte IODIS Bit Number Bit Mnemonic Description 7 0 This bit should not be set. Card I/O isolation Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 ...
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Table 12. STATUS (Status Byte) Bit Number Table 13. TIMER 1 (Timer MSB) Number Reset value = 0x00000001 4234G–SCR–01/ CC8 CC4 CARDIN Bit Mnemonic Description Card CC8 7 CC8 This bit provides the actual level on the ...
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Table 14. TIMER 0 (Timer LSB) Number Reset value = 0x10010000 Table 15. CAPTURE 1 (Capture MSB) Number Reset value = 0x00000000 Table 16. CAPTURE 0 (Capture LSB) Number Reset value = 0x00000000 AT83C24 Bit 7 ...
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... EVCC connected to host power supply: from 1.6V to 5.5V -40°C to +85° CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24B CLASS B card supplied with CVCC = 2.8V to 3.2V CLASS C card supplied with CVCC = 1.68V to 1.92V Table 17. Core (VCC) Symbol ...
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Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT) (Continued) Symbol Parameter V Output Low-voltage (I/O, C4, C8, PRES/INT) OL Output High Voltage (C4, C8, PRES/INT I/O depends on external pull up ...
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... AT83C24 Unit Test Conditions 0 < Icard < 60mA C =10µF L for AT83C24B mV 0 < Icard < 65mA C = 3.3µF L for AT83C24NDS Max. charge 40 nA.s V Max. duration 400 ns Max. Icard variation 200 mA V AT83C24B V AT83C24NDS > V Icard = 0, VCC PFDP µ ...
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Table 21. Smart Card Class B Symbol Parameter T CVCC 0 to Valid VLH Notes: 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz), Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR ...
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Table 23. Smart Card Clock (CCLK pin) (Continued) Symbol Parameter Rise and Fall Slew rate Low level voltage stability (taking into account PCB design) High level voltage stability (taking into account PCB design) CCLK Smart card clock frequency Table 24. ...
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Table 25. Smart Card RST (CRST pin) Symbol Parameter V Output Low-voltage OL V Output High Voltage OH I Output High Current Rise and Fall time R F Low level voltage stability (taking into account PCB design) ...
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... Typical Application Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24B ( AT83C24B if needed) EVCC Host MICROCONTROLLER XTAL1 XTAL2 MHz VSS VSS Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor VCC See note for I/O pull up SDA, ...
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Typical NDS Application Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS. EVCC VCC TWI RST INT0 Px.y Px.y Px.y Px.y Host MICROCONTROLLER XTAL1 XTAL2 18.432 or 27MHz VSS VSS Note: AT83C24 36 See note ...
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... Ordering Information Part Number AT83C24B-PRTIL AT83C24B-PRRIL AT83C24B-PRTIM AT83C24B-PRRIM AT83C24B-TISIL AT83C24B-TIRIL AT83C24B-TISIM AT83C24B-TIRIM AT83C24NDS-PRTIL AT83C24NDS-PRRIL AT83C24NDS-PRTIM AT83C24NDS-PRRIM AT83C24NDS-TISIL AT83C24NDS-TIRIL AT83C24NDS-TISIM AT83C24NDS-TIRIM AT83C24B-PRTUL AT83C24B-PRRUL AT83C24B-PRTUM AT83C24B-PRRUM AT83C24B-TISUL AT83C24B-TIRUL AT83C24B-TISUM AT83C24B-TIRUM AT83C24NDS-PRTUL AT83C24NDS-PRRUL AT83C24NDS-PRTUM AT83C24NDS-PRRUM 4234G–SCR–01/07 Supply Voltage Temperature Range ( 5.5V Industrial ( ...
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Part Number AT83C24NDS-TISUL AT83C24NDS-TIRUL AT83C24NDS-TISUM AT83C24NDS-TIRUM Note: 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS. 2. Refer to index mark for proper placement. AT83C24 38 Supply Voltage Temperature Range ( 5.5V Industrial & ...
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Package Drawings QFN28 4234G–SCR–01/07 AT83C24 39 ...
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SO28 ...
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... QFN28 new package drawing. 4234D-04/ Clock input parameters for AT83C24 and AT83C24NDS. 4234E - 09/04 Changes from 1. Updated green product ordering information. 4234E - 09/04 to 4234F - 10/05 Changes from 1. Addition of Warm reset description. 4234F - 10/ Update of AT83C24 for AT83C24B and AT83C24NDS. 4234G - 12/05 4234G–SCR–01/07 AT83C24 41 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...