AT89C51RB2-RLTCM ATMEL [ATMEL Corporation], AT89C51RB2-RLTCM Datasheet
AT89C51RB2-RLTCM
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AT89C51RB2-RLTCM Summary of contents
Page 1
... The Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. Power Supply ...
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... In power-down mode, the RAM is saved and all other functions are inoperative. The added features of the AT89C51RB2/RC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, and smart card readers ...
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... SFR Mapping 4180B–8051–04/03 The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
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... Interrupt Priority Control High 1 IPL1 B2h Interrupt Priority Control Low 1 Table 5. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 AT89C51RB2/RC2 SMOD1 SMOD0 - - DPU - M0 XRS2 ...
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... CCAP3H5 CCAP3H4 CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 AT89C51RB2/RC2 TR0 IE1 IT1 IE0 M01 GATE0 C/T0# M10 - - WTO2 WTO1 EXEN2 TR2 C/T2 T2OE 3 2 ...
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... SPI Status SPDAT C5h SPI Data Table 10. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register AT89C51RB2/RC2 FE/SM0 SM1 SM2 REN BRR SPR2 SPEN SSDIS ...
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... KBLS 0000 0000 XXX0 0000 0000 0000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT89C51RB2/RC2 5/D 6/E 7/F CCAPL3H CCAPL4H XXXX XXXX CCAPL3L CCAPL4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 TH2 0000 0000 ...
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... P3.4/ P3.5/T1 16 P3.6/ P3.7/RD 18 XTAL2 XTAL1 20 21 VSS P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI *NIC: No Internal Connection AT89C51RB2/RC2 8 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P1.5/CEX2/MISO P0.5/AD5 P1.6/CEX3/SCK P1.7/CEx4/MOSI P0.6/AD6 P0.7/AD7 EA ALE/PROG PSEN P2.7/AD15 P2.6/AD14 P2.5/AD13 P2.4/AD12 P2.3/AD11 P2.2/AD10 P2.1/AD9 P2.0/AD8 ...
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... As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address Byte during memory programming and verification. Alternate functions for AT89C51RB2/RC2 Port 1 include: 40 I/O P1.0: Input/Output I/O T2 (P1 ...
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... RST 9 10 ALE/PROG 30 33 AT89C51RB2/RC2 10 Type Name and Function I/O CEX4: Capture/Compare External I/O for PCA Module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. ...
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... PSEN is not activated during fetches from internal program memory External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset. AT89C51RB2/RC2 11 ...
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... Oscillator Registers AT89C51RB2/RC2 12 To optimize the power consumption and execution time needed for a specific task, an internal, prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 13. CKRL Register CKRL – Clock Reload Register (97h CKRL7 CKRL6 ...
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... CLKPERIPH 2 255 CKRL – Mode, for CKRL<>0xFF then: F OSC ---------------------------------------------- - CPU × ( CLKPERIPH 4 255 CKRL – AT89C51RB2/RC2 1 CLK PERIPH 0 CLK CPU Idle CKRL = 0xFF (Standard C51 feature) OSC /1020 (Standard Mode) /510 (X2 Mode) /2 (Standard Mode) (X2 Mode Peripheral Clock ...
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... ALE disabling • Some enhanced features are also located in the UART and the timer 2 The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
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... The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register (Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast periph- eral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. AT89C51RB2/RC2 X1 Mode 15 ...
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... AT89C51RB2/RC2 16 Table 15. CKCON0 Register CKCON0 - Clock Control Register (8Fh WDX2 PCAX2 Bit Bit Number Mnemonic Description 7 Reserved Watchdog Clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit 6 WDX2 has no effect). Cleared to select 6 clock periods per peripheral clock cycle. ...
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... SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Reset Value = XXXX XXX0b Not bit addressable AT89C51RB2/RC2 ...
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... Register (DPTR) Figure 6. Use of Dual Pointer 7 DPS AUXR1(A2H) AT89C51RB2/RC2 18 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1 ...
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... A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the Byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 20 INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is ’ ...
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... Table 18. Expanded RAM Part Number XRAM Size AT89C51RB2/RC2 1024 The AT89C51RB2/RC2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable only ...
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... AT89C51RB2/RC2 22 • Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions ...
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... ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65) Not bit addressable AT89C51RB2/RC2 XRS1 XRS0 EXTRAM ...
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... Auto-reload Mode AT89C51RB2/RC2 24 The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects F operation) or external pin T2 (counter operation) as the timer clock input ...
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... To start the timer, set TR2 run control bit in T2CON register possible to use Timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 26 Figure 9. Clock-Out Mode C/ FCLK PERIPH T2 T2EX TR2 T2CON 2 TL2 TH (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 4180B–8051–04/03 ...
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... Timer 2 Capture/Reload Bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. 0 CP/RL2# Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1. Reset Value = 0000 0000b Bit addressable AT89C51RB2/RC2 TCLK EXEN2 TR2 C/T2 CP/RL2# ) ...
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... AT89C51RB2/RC2 28 Table 21. T2MOD Register T2MOD – Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...
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... CPS1 and CPS0 bits in the CMOD register (Table 22) and can be programmed to run at: peripheral clock frequency (F • 1/6 the peripheral clock frequency (F • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C51RB2/RC2 ÷ ÷ External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1 ...
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... Figure 10. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle AT89C51RB2/RC2 30 CH 16-bit Up/Down Counter CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA Modules overflow It CL CMOD ECF 0xD9 CCON 0xD8 4180B–8051–04/03 ...
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... ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1, etc. ) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 32 Table 23. CCON Register CCON – PCA Counter Control Register (D8h Bit Bit Number Mnemonic Description PCA Counter Overflow Flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF CMOD is set. CF may be set by either hardware or software but can only be cleared by software ...
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... CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn. 6) when set enables the comparator function. Table 24 shows the CCAPMn settings for the various PCA functions. AT89C51RB2/RC2 CCON 0xD8 To Interrupt Priority Decoder IE ...
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... AT89C51RB2/RC2 34 Table 24. CCAPMn Registers (n = 0-4) CCAPM0 – PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 – PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 – PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 – PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 – PCA Module 4 Compare/Capture Control Register (0DEh) ...
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... Bit Bit Number Mnemonic Description PCA Module n Compare/Capture Control CCAPnH Value Reset Value = 0000 0000b Not bit addressable AT89C51RB2/RC2 TOGn PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger ...
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... AT89C51RB2/RC2 36 Table 27. CCAPnL Registers (n = 0-4) CCAP0L – PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L – PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L – PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L – PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L – PCA Module 4 Compare/Capture Control Register Low (0EEh) ...
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... CCAPnH). If the CCFn bit for the Module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (see Figure 12). CR CCF4 CCF3 CCF2 CCF1 CCF0 Capture CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C51RB2/RC2 CCON 0xD8 PCA IT PCA Counter/Timer CH CL CCAPnH ...
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... CCAPnH Enable 1 0 AT89C51RB2/RC2 38 The PCA Modules can be used as software timers by setting both the ECOM and MAT bits in the Modules CCAPMn register. The PCA timer will be compared to the Module’s capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the Module are both set (see Figure 13) ...
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... Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. AT89C51RB2/RC2 CCF4 CCF3 CCF2 CCF1 CCF0 Match CAPNn MATn TOGn PWMn ECCFn ...
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... Pulse Width Modulator Mode PCA Watchdog Timer AT89C51RB2/RC2 40 All of the PCA Modules can be used as PWM outputs. Figure 15 shows the PWM func- tion. The frequency of the output depends on the source for the PCA timer. All of the Modules will have the same frequency of output because they all share the PCA timer. ...
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... Modules would not be a good idea. Thus, in most appli- cations the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. AT89C51RB2/RC2 41 ...
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... Serial I/O Port Framing Error Detection AT89C51RB2/RC2 42 The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates ...
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... The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b AT89C51RB2/RC2 Data Byte Ninth Stop bit ...
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... Broadcast Address Reset Addresses AT89C51RB2/RC2 44 The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t care bit; for slaves B and C, bit 1.To commu- nicate with slave A only, the master must send an address where bit 0 is clear (e. g. ...
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... The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 19. Baud Rate Selection TIMER1 TIMER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 0 TIMER_BRG_TX TIMER2 1 TCLK INT_BRG AT89C51RB2/RC2 Clock 1 RBCK ...
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... Internal Baud Rate Generator (BRG) Figure 20. Internal Baud Rate CLK PERIPH BRR AT89C51RB2/RC2 46 Table 32. Baud Rate Selection Table UART TCLK RCLK (T2CON) (T2CON) (BDRCON When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register ...
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... Receive Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0, see Figure 17. and Figure 18 in the other modes. Reset Value = 0000 0000b Bit addressable AT89C51RB2/RC2 REN TB8 RB8 Mode Description ...
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... UART Registers AT89C51RB2/RC2 48 Table 34. Example of Computed Value When SMOD1 = 1, SPD = 16. 384 MHz OSC Baud Rates BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 35. Example of Computed Value When SMOD1 = 0, SPD = 16. 384 MHz ...
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... Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 39. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah Reset Value = 0000 0000b AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 50 Table 40. T2CON Register T2CON – Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1 ...
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... Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT89C51RB2/RC2 POF GF1 ...
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... AT89C51RB2/RC2 52 Table 42. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved 6 - The value read from this bit is indeterminate. Do not set this bit Reserved ...
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... Individual Enable 4180B–8051–04/03 The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI inter- rupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 21 ...
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... Registers AT89C51RB2/RC2 54 A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 43. Priority Level Bit Values IPH two interrupt requests of different priority levels are received simultaneously, the request of higher-priority level is serviced ...
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... Timer 0 Overflow Interrupt Enable Bit 1 ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External Interrupt 0 Enable Bit 0 EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable AT89C51RB2/RC2 ET1 EX1 ET0 0 EX0 55 ...
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... AT89C51RB2/RC2 56 Table 45. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority Bit 6 PPCL see PPCH for priority level. Timer 2 Overflow Interrupt Priority Bit ...
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... External Interrupt 0 Priority High Bit PX0H PX0L PX0H Reset Value = X000 0000b Not bit addressable AT89C51RB2/RC2 PSH PT1H PX1H PT0H Priority Level Lowest Highest Priority Level Lowest Highest Priority Level Lowest Highest Priority Level ...
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... AT89C51RB2/RC2 58 Table 47. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI Interrupt Enable Bit Cleared to disable SPI interrupt. 2 SPI Set to enable SPI interrupt Reserved Keyboard Interrupt Enable Bit 0 KBD Cleared to disable keyboard interrupt. ...
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... SPI Interrupt Priority Bit 2 SPIL see SPIH for priority level. Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority Bit 0 KBDL see KBDH for priority level. Reset Value = XXXX X000b Bit addressable AT89C51RB2/RC2 SPIL - 0 KBDL 59 ...
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... AT89C51RB2/RC2 60 Table 49. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
Page 61
... Table 50. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard 9 9 AT89C51RB2/RC2 Interrupt Request Reset INT0 IE0 Timer 0 TF0 INT1 IE1 Timer 1 IF1 UART RI+TI Timer 2 TF2+EXF2 PCA CF + CCFn (n = 0-4) KBDIT SPI SPIIT Vector Address 0000h 0003h ...
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... Power Reduction Mode AT89C51RB2/RC2 62 The AT89C51RB2/RC2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes. ...
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... Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set. Must be cleared by software. Keyboard Line 0 Flag Set by hardware when the Port line 0 detects a programmed level. It generates a 0 KBF0 Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set. Must be cleared by software. Reset Value = 0000 0000b AT89C51RB2/RC2 KBF4 KBF3 KBF2 KBF1 1 ...
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... AT89C51RB2/RC2 64 Table 52. KBE Register KBE - Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard Line 7 Enable Bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. Keyboard Line 6 Enable Bit ...
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... Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard Line 0 Level Selection Bit 0 KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value = 0000 0000b AT89C51RB2/RC2 KBLS4 KBLS3 KBLS2 KBLS1 ...
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... Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51RB2/RC2 66 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: • ...
Page 67
... AT89C51RB2/RC2 Clock Rate Baud Rate Divisor (BD) Don’t Use No BRG F /4 CLK PERIPH F /8 CLK PERIPH F /16 CLK PERIPH F /32 CLK PERIPH F /64 CLK PERIPH F /128 128 CLK PERIPH Don’ ...
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... Functional Description Operating Modes AT89C51RB2/RC2 68 Figure 25 shows a detailed structure of the SPI Module. Figure 25. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS MSTR SPI Interrupt Request The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode ...
Page 69
... The SPI Module should be configured as a Slave before it is enabled (SPEN set). 3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. 4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). AT89C51RB2/RC2 MISO 8-bit Shift register MOSI SCK SS ...
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... Figure 28. Data Transmission Format (CPHA = 1) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 29. CPHA/SS Timing MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) AT89C51RB2/RC2 MSB bit6 bit5 bit4 MSB bit6 bit5 bit4 1 2 ...
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... SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 30 gives a logical view of the above statements. AT89C51RB2/RC2 Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) ...
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... Registers Serial Peripheral Control Register (SPCON) AT89C51RB2/RC2 72 Figure 30. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs. • ...
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... Set by hardware to indicate that the SS pin is at inappropriate logic level. Reserved 3 - The value read from this bit is indeterminate. Do not set this bit Reserved 2 - The value read from this bit is indeterminate. Do not set this bit. AT89C51RB2/RC2 SPR1 SPR0 Serial Peripheral Rate 0 0 Invalid ...
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... Serial Peripheral DATa Register (SPDAT) AT89C51RB2/RC2 74 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable The Serial Peripheral Data Register (Table 58 read/write buffer for the receive data register ...
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... WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C51RB2/RC2 , where T CLK PERIPH CLK PERIPH 7 counter has been added to extend the Time-out = 12 MHz. To manage this feature, see OSCA 4 3 ...
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... WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
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... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 61 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...
Page 78
... Cold Reset AT89C51RB2/RC2 78 Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addi- tion to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”. ...
Page 79
... RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit kΩ resis- tor must be added as shown Figure 32. Figure 32. Reset Circuitry for WDT Reset-out Usage VDD + RST VDD 1K RST VSS AT89C51RB2/RC2 (1) VDD Rise Time 10 ms 100 ms 1.2 µF 3.9 µF From WDT VDD Reset Source P ...
Page 80
... Prevent Flash Corruption Idle Mode Power-down Mode AT89C51RB2/RC2 80 An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. ...
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... Power Down Internal Power Down External 4180B–8051–04/03 be the one following the instruction that puts the AT89C51RB2/RC2 into Power-down mode. Power-down Phase Oscillator Restart Phase Exit from Power-down by reset redefines all the SFRs, exit from Power-down by exter- nal interrupt does no affect the SFRs. ...
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... Power-off Flag AT89C51RB2/RC2 82 The Power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could be generated by an exit from Power-down. CC The Power-off flag (POF) is located in PCON register (Table 63). POF is set by hard- ware when V rises from 0 to its nominal voltage ...
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... Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. AT89C51RB2/RC2 XRS1 XRS0 EXTRAM ...
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... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51RB2/RC2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. pins of CC supply ...
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... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte (HSB). Table 65. Hardware Security Byte (HSB) 7 ...
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... Default Values Software Registers AT89C51RB2/RC2 86 Table 66. Program Lock Bits Program Lock Bits Security Level LB0 LB1 LB2 Protection Description program lock features enabled. MOVC instruction executed from external program memory is disabled from fetching code Bytes from internal memory sampled and ...
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... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 69. AT89C51RB2/RC2 Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable F7h AT89C51RB2/RC2 32KB FBh AT89C51RB2/RC2 16 KB AT89C51RB2/RC2 32KB, EFh Revision 0 AT89C51RB2/RC2 16 KB, FFh Revision LB1 0 LB0 87 ...
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... After ISP After ISP Programming In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address space is filled by internal Flash. When the EA pin is high, the processor fetches instructions from internal program Flash. Bus expansion for accessing program memory from 16K or 32K upward automatic since external instruction fetches occur automatically when the program counter exceeds 3FFFh (16K) or 7FFFh (32K) ...
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... Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 35. Diagram Context Description Access via Specific Protocol Access From User Application ISP: In-system Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit HW : Hardware Byte AT89C51RB2/RC2 Bootloader Flash Memory 89 ...
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... Functional Description Figure 36. Bootloader Functional Description Exernal Host with Specific Protocol Communication AT89C51RB2/RC2 90 ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device ...
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... The BLJB test is perform by hardware to prevent any program execution. The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value custumer bootloader in user Flash. SBV Note: The costumer bootloader is called by JMP [SBV]00h instruction. AT89C51RB2/RC2 91 ...
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... Boot Process Figure 37. Bootloader process PC = 0000h USER APPLICATION AT89C51RB2/RC2 92 RESET If BLJB = 0 then ENBOOT bit (AUXR1) is set else ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE = 1 or not connected) FCON = 00h Hardware Condition? FCON = F0h BLJB = 1 BLJB!= 0 ENBOOT = 0 ? BLJB = 0 ENBOOT = 1 F800h ...
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... ASCII hexadecimal digits to one Byte of binary, and including the Reclen field to and including the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. AT89C51RB2/RC2 Record Type Data or Info Checksum ...
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... Functional Description Software Security Bits (SSB) AT89C51RB2/RC2 94 The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) This is the default level. ...
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... The host initializes the communication by sending a ’U’ character to help the bootloader to compute the baudrate (autobaud). Figure 38. Initialization Host Init Communication If (not received "U") Else Communication Opened AT89C51RB2/RC2 Bootloader "U" Performs Autobaud Sends Back ‘U’ Character "U" 95 ...
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... This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP featur e requir es that an initial char acter ( an uppercase U) be sent to the AT89C51RB2/RC2 to establish the baud rate. Table 72 shows the autobaud capability. 2 2.4576 3 3 ...
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... Config Byte Programming Data Frame • Baud Rate Frame Write Command ’X’ & CR & LF ’P’ & CR & LF ’.’ & CR & LF AT89C51RB2/RC2 Bootloader If (not received ":") Else Sends echo and start reception Gets frame, and sends back ec for each received Byte ...
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... Example AT89C51RB2/RC2 98 Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 BOOTLOADER : 01 0010 Programming Atmel function (write SSB to level 0000 HOST BOOTLOADER : 02 0000 F5 Writing Frame (write BSB to 55h) HOST : 03 0000 BOOTLOADER : 03 0000 ...
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... BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF Blank Check with checksum error HOST : 05 0000 04 0000 7FFF 01 70 BOOTLOADER : 05 0000 04 0000 7FFF AT89C51RB2/RC2 Bootloader Wait Blank Check Command Checksum error Send Checksum error Flash blank Send COMMAND_OK Send first Address ...
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... COMMAND ABORTED Wait Display Data All data read COMMAND FINISHED Note: The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command. AT89C51RB2/RC2 100 Display Command ’X’ & CR & LF Send Checksum Error ’L’ & CR & LF ...
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... HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF Atmel Read function (read Bootloader version) HOST : 02 0000 0000 Value . CR LF BOOTLOADER AT89C51RB2/RC2 (16 data) (16 data data) Bootloader Wait Read Command Checksum error Send Checksum error RD_WR_SECURITY Send Security error ...
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... ISP Commands Summary AT89C51RB2/RC2 102 Table 73. ISP Commands Summary Command Command Name Data[0] 00h Program Data 03h Write Function Data[0:1] = start address Data [2:3] = end address 04h Display Function Data[4] = 00h -> Display data Data[4] = 01h -> Blank check 05h Read Function Data[1] Command Effect Program Nb Data Byte ...
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... XXh 0001h XXh 0000h XXh 0004h XXh 0001h XXh 0002h XXh AT89C51RB2/RC2 Returned Value Command Effect Read Manufacturer identifier ID Read Device identifier 1 ACC=Device ID 2 Read Device identifier 2 ACC=Device ID 3 Read Device identifier 3 Erase block 0 (from 0x0000 to 0x1FFF) Erase block 1 (from 0x2000 to 0x3FFF) ...
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... Fuse value PROGRAM BLJB 0Ah FUSE 00h or 01h READ BOOT ID1 0Eh XXh READ BOOT ID2 0Eh XXh READ BOOT VERSION 0Fh XXh AT89C51RB2/RC2 104 DPTR0 DPTR1 Returned Value ACC=Manufacturer 0000h XXh ID 0001h XXh ACC= Device ID 1 0002h XXh ACC=Device ID 2 ...
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... 1 AT89C51RB2/RC2 Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions may affect device reliability ...
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... For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. 9. Flash Retention is guaranteed with the same formula for V AT89C51RB2/RC2 106 =2.7V to 5.5V MHz (Continued) Min Typ ...
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... CC (6) ( (5) 50 200 (5) 10 0.4 x Frequency (MHz would be slightly higher if a crystal oscillator used (see Figure RST = V (see Figure 45 must be externally limited as follows: OL AT89C51RB2/RC2 Max Unit Test Conditions -10 µA ...
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... V OL than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. AT89C51RB2/RC2 108 may exceed the related specification. Pins are not guaranteed to sink current greater OL Figure 44. I ...
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... Address Hold after ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In PLIV T Input Instruction Hold after PSEN PXIX T Input Instruction Float after PSEN PXIZ T Address to Valid Instruction In AVIV T PSEN Low to Address Float PLAZ AT89C51RB2/RC2 109 ...
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... AT89C51RB2/RC2 110 Table 76. AC Parameters for a Fix Clock Symbol -M Min LHLL T 5 AVLL T 5 LLAX T LLIV T 5 LLPL T 50 PLPH T PLIV T 0 PXIX T PXIZ T AVIV T PLAZ Table 77. AC Parameters for a Variable Clock Standard Symbol Type Clock T Min LHLL ...
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... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C51RB2/RC2 CLCL T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 111 ...
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... AT89C51RB2/RC2 112 Table 79. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T 155 QVWH T 10 WHQX T 0 RLAZ T 5 WHLH -L Max Min Max 125 125 ...
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... Min 0 WHQX T Max x x RLAZ T Min 0 WHLH T Max 0 WHLH T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 AT89C51RB2/RC2 X Parameter for - X Parameter for - M Range L Range ...
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... External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode AT89C51RB2/RC2 114 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Table 80. Symbol Description Symbol Parameter T Serial port clock cycle time XLXL T Output data set-up to clock rising edge ...
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... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20mA. occurs Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT89C51RB2/RC2 ...
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... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51RB2/RC2 116 STATE5 STATE6 ...
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... Ordering Information Table 83. Possible Order Entries Part Number AT89C51RB2-3CSIM AT89C51RB2-SLSCM AT89C51RB2-SLSIM AT89C51RB2-SLSIL AT89C51RB2-RLTCM AT89C51RB2-RLTIM AT89C51RB2-RLTIL AT89C51RC2-3CSCM AT89C51RC2-3CSIM AT89C51RC2-SLSCM AT89C51RC2-SLSIM AT89C51RC2-SLSIL AT89C51RC2-RLTCM AT89C51RC2-RLTIM AT89C51RC2-RLTIL 4180B–8051–04/03 Memory Size Supply Voltage 16 KBytes 5V 16 KBytes 5V 16 KBytes 5V 16 KBytes 3V 16 KBytes 5V 16 KBytes ...
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... Package Information PDIL40 AT89C51RB2/RC2 118 4180B–8051–04/03 ...
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... VQFP44 PLC44 4180B–8051–04/03 AT89C51RB2/RC2 119 ...
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... AT89C51RB2/RC2 120 4180B–8051–04/03 ...
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... Datasheet Change Log Changes from 4180A-08/02 to 4180B- 04/03 4180B–8051–04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 2. Added note on Flash retention formula for V Standard Voltage”, page 105. AT89C51RB2/RC2 , in Section “DC Parameters for IH1 121 ...
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Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 2 SFR Mapping ......................................................................................... 3 Pin Configurations ................................................................................ 8 Oscillator ............................................................................................. 12 Enhanced Features ............................................................................. 14 Dual Data Pointer Register (DPTR) ................................................... 18 Expanded RAM (XRAM) ...................................................................... 21 ...
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UART Registers.................................................................................................. 48 Interrupt System ................................................................................. 53 Registers............................................................................................................. 54 Interrupt Sources and Vector Addresses............................................................ 61 Keyboard Interface ............................................................................. 62 Registers............................................................................................................. 63 Serial Port Interface (SPI) ................................................................... 66 Features.............................................................................................................. 66 Signal Description............................................................................................... 66 Functional Description ........................................................................................ 68 Hardware Watchdog Timer ...
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AC Parameters ................................................................................................. 109 Ordering Information ........................................................................ 117 Package Information ........................................................................ 118 PDIL40.............................................................................................................. 118 VQFP44 ............................................................................................................ 119 PLC44............................................................................................................... 119 Datasheet Change Log ..................................................................... 121 Changes from 4180A-08/02 to 4180B-04/03 .................................................... 121 Table of Contents .................................................................................. i 4180B–8051–04/03 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem ...