DS8906N NSC [National Semiconductor], DS8906N Datasheet

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DS8906N

Manufacturer Part Number
DS8906N
Description
AM/FM Digital Phase-Locked Loop Synthesizer
Manufacturer
NSC [National Semiconductor]
Datasheet
C 1995 National Semiconductor Corporation
DS8906 AM FM Digital Phase-Locked Loop Synthesizer
General Description
The DS8906 is a PLL synthesizer designed specifically for
use in AM FM radios It contains the reference oscillator a
phase comparator a charge pump a 120 MHz ECL I
dual modulus programmable divider and a 20-bit shift regis-
ter latch for serial data entry The device is designed to
operate with a serial data controller generating the neces-
sary division codes for each frequency and logic state infor-
mation for radio function inputs outputs
The Colpitts reference oscillator for the PLL operates at 4
MHz A chain of dividers is used to generate a 500 kHz
clock signal for the external controller Additional dividers
generate a 12 5 kHz reference signal for FM and a 500 Hz
reference signal for AM SW One of these reference signals
is selected by the data from the controller for use by the
phase comparator Additional dividers are used to generate
a 50 Hz timing signal used by the controller for ‘‘time-of-
day’’
Data is transferred between the frequency synthesizer and
the controller via a 3 wire bus system This consists of a
data input line an enable line and a clock line When the
enable line is low data can be shifted from the controller
into the frequency synthesizer When the enable line is tran-
sitioned from low to high data entry is disabled and data
present in the shift register is latched
From the controller 22-bit data stream the first 2 bits ad-
dress the device permitting other devices to share the same
bus Of the remaining 20-bit data word the next 14-bits are
used for the PLL divide code The remaining 6 bits are con-
nected via latches to output pins These 6 bits can be used
to drive radio functions such as gain mute FM AM LW and
SW only These outputs are open collector Bit 18 is used
internally to select the AM or FM local oscillator input and to
select between the 500 Hz and 12 5 kHz reference A high
level at bit 18 indicates FM and a low level indicates AM
The PLL consists of a 14-bit programmable I
ECL phase comparator an ECL dual modulus (p p
prescaler and a high speed charge pump The programma-
ble divider divides by (N
into the shift register (bits 1–14 after address) It is clocked
by the AM input via an ECL
63 64 prescaler from the FM input The AM input will work
at frequencies up to 8 MHz while the FM input works up to
120 MHz The AM band is tuned with a frequency resolution
of 500 Hz and the FM band is tuned with a resolution of 12 5
kHz The buffered AM and FM inputs are self-biased and
can be driven directly by the VCO thru a capacitor The ECL
phase comparator produces very accurate resolution of the
phase difference between the input signal and the reference
oscillator
TRI-STATE is a registered trademark of National Semiconductor Corp
a
d
1) N being the number loaded
TL F 5775
7 8 prescaler or through a
2
L divider an
a
2
d
1)
L
The high speed charge pump consists of a switchable con-
stant current source (
current sink (
charge pump will source current and sink current if the VCO
frequency is high
A separate V
oscillator and reference chain to provide controller clocking
frequencies when the balance of the PLL is powered down
Features
Y
Y
Y
Y
Y
Y
Y
Connection Diagram
Uses inexpensive 4 MHz reference crystal
F
thesis at FM frequencies
FM resolution of 12 5 kHz allows usage of 10 7 MHz
ceramic filter distribution
Serial data entry for simplified control
50 Hz output for ‘‘time-of-day’’ reference with separate
low power supply (V
6-open collector buffered outputs for band switching
and other radio functions
Separate AM and FM inputs AM input has 15 mV (typi-
cal) hysteresis
IN
capability greater than 120 MHz allows direct syn-
CCM
See NS Package Number N20A
a
0 3 mA) If the VCO frequency is low the
Order Number DS8906N
pin (typically drawing 1 5 mA) powers the
Dual-In-Line Package
b
CCM
0 3 mA) and a switchable constant
Top View
)
RRD-B30M105 Printed in U S A
TL F 5775 – 1
July 1986

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DS8906N Summary of contents

Page 1

... Y and other radio functions Separate AM and FM inputs AM input has 15 mV (typi- Y cal) hysteresis Connection Diagram Dual-In-Line Package 2 L divider Top View Order Number DS8906N See NS Package Number N20A July 1986 ) TL F 5775 – 1 RRD-B30M105 Printed ...

Page 2

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (V ) CC1 (V ) CCM Input Voltage Output Voltage DC Electrical Characteristics Symbol Parameter V ...

Page 3

AC Electrical Characteristics Symbol Parameter t Minimum Time After ENABLE EN1CLK Goes High Before an Unused Positive CLOCK Edge May Occur t Minimum CLOCK High CLKH Pulse Width t Minimum CLOCK Low CLKL Pulse Width t Minimum DATA Setup Time ...

Page 4

Schematic Diagrams (DS8906 AM FM PLL Typical Input Output Schematics) (Continued 5775– 7 Timing Diagrams AM FM Frequency Synthesizer (Scan Mode) Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and ...

Page 5

Applications Information SERIAL DATA ENTRY INTO THE DS8906 Serial information entry into the DS8906 is enabled by a low level on the ENABLE input One binary bit is then accepted from the DATA input with each positive transition of the ...

Page 6

Typical Application Electronically Tuned Radio Controller System Direct Drive LED 5775– 12 ...

Page 7

Logic Diagram Sections operating from V supply CCM Address ( PLL Synthesizer 5775 – 13 ...

Page 8

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Molded Dual-In-Line Package (N) Order Number DS8906N NS Package Number N20A 2 A critical component is any component of a life ...

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