TH8056KDCA MELEXIS [Melexis Microelectronic Systems], TH8056KDCA Datasheet - Page 11

• Manufacturer Part Number: TH8056KDCA
• Description: Enhanced Single Wire CAN Transceiver
• Manufacturer: MELEXIS [Melexis Microelectronic Systems]

3. Functional Description
3.1 TxD Input pin
Logic command to transmit on the single wire CAN bus
TxD Polarity
If the TxD pin is driven to a logic low state while Mode 0,1 pins are in the 0,0 or sleep state, the transceiver
cannot drive the CAN Bus pin to the dominant state.
The transceiver provides an internal pull up on the TxD pin, which will cause the transmitter to default to the
bus recessive state, when TxD is not driven.
TxD input signals are standard CMOS logic levels for 3.3V and 5V supply voltages.
Time-out feature
In case of a faulty blocked dominant TxD input signal the CANH output is switched off automatically after the
specified TxD time-out reaction time to prevent a dominant bus. The transmission is continued by next TxD L
to H transition without delay.
3.2 Mode 0 and Mode 1 pins
Select transceiver operating modes
The transceiver provides a weak internal pull-down current on each of these pins, which causes the
transceiver to default to sleep mode when they are not driven. The Mode input signals are standard CMOS
logic level for 3.3V and 5V supply voltages.
Figure 5 – Truth Table
Mode 0 = 0, Mode 1 = 0 – Sleep mode
Transceiver is in low-power state, waiting for wake-up via high-voltage signal or by mode pins change to any
state other than 0,0. In this state, the CAN Bus pin is not in the dominant state regardless of the state of the
TxD pin.
Mode 0 = 1, Mode 1 = 0 – High-Speed mode
This mode allows high-speed download with bitrates up to 100Kbit/s. The output waveshaping circuit is
disabled in this mode. Bus transmitters which require communicating in high-speed mode are able to drive
reduced bus resistance during this mode.
Note: High-speed mode is only allowed with connected tool resistance in parallel to the network load. Otherwise the stability of the
output signal is not guaranteed because of the slew rate enhancement for the required rise times .
TH8056 – Datasheet
3901008056
M0
H
H
L
L
TxD = logic 1 (or floating) on this pin produces an undriven or recessive bus state (low bus voltage)
TxD = logic 0 on this pin produces either a bus normal or a bus high-voltage dominant state
depending on the transceiver mode state (high bus voltage)
M1
H
H
L
L
Mode
Sleep Mode
High-Speed
High-Voltage Wake-Up
Normal Mode
Page 11 of 26
Enhanced Single Wire CAN Transceiver
TH8056
March 2007
Rev 012