MXB7846EEE MAXIM [Maxim Integrated Products], MXB7846EEE Datasheet - Page 15

• Manufacturer Part Number: MXB7846EEE
• Description: 2.375V to 5.25V, 4-Wire Touch-Screen Controller with Internal Reference and Temperature Sensor
• Manufacturer: MAXIM [Maxim Integrated Products]

Start a conversion by clocking a control byte into DIN
(Table 3) with CS low. Each rising edge on DCLK
clocks a bit from DIN into the MXB7846’s internal shift
register. After CS falls, the first arriving logic 1 bit
defines the control byte’s START bit. Until the START bit
arrives, any number of logic 0 bits can be clocked into
DIN with no effect.
The MXB7846 is compatible with SPI/QSPI/MICROWIRE
devices. For SPI, select the correct clock polarity and
sampling edge in the SPI control registers of the micro-
controller: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. The simplest software interface requires
only three 8-bit transfers to perform a conversion (one 8-
bit transfer to configure the ADC, and two more 8-bit
transfers to read the conversion result; Figure 9).
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 2MHz:
1) Set up the control byte and call it TB. TB should be
2) Use a general-purpose I/O line on the CPU to pull
3) Transmit TB and simultaneously receive a byte; call
4) Transmit a byte of all zeros ($00 hex) and simultane-
5) Transmit a byte of all zeros ($00 hex) and simultane-
6) Pull CS high.
with Internal Reference and Temperature Sensor
Table 3. Control Byte Format
2.375V to 5.25V, 4-Wire Touch-Screen Controller
in the format: 1XXXXXXX binary, where X denotes
the particular channel, selected conversion mode,
and power mode (Tables 3, 4).
CS low.
it RB1.
ously receive byte RB2.
ously receive byte RB3.
START
BIT 7
BIT
7
6
5
4
3
2
1
0
SER/DFR
START
NAME
MODE
BIT 6
______________________________________________________________________________________
PD1
PD0
A2
A2
A1
A0
Start bit
Address (Tables 1 and 2)
Conversion resolution: 1 = 8 bits, 0 = 12 bits
Conversion mode: 1 = single ended, 0 = differential
Power-down mode (Table 4)
Simple Software Interface
BIT 5
A1
BIT 4
A0
MODE
BIT 3
Figure 9 shows the timing for this sequence. Byte RB2
and RB3 contain the result of the conversion, padded
with four trailing zeros. The total conversion time is a
function of the serial-clock frequency and the amount of
idle timing between 8-bit transfers.
The MXB7846 outputs data in straight binary format. Data
is clocked out on the falling edge of the DCLK MSB first.
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
BUSY pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 DCLK falling edges. BUSY and DOUT go into a
high-impedance state when CS goes high.
The conversion must complete in 500µs or less; if not,
droop on the sample-and-hold capacitors can degrade
conversion results.
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on DCLK’s falling edge, after the eighth bit of
the control byte is clocked into DIN.
The first logic 1 clocked into DIN after bit 6 of a conver-
sion in progress is clocked onto the DOUT pin and is
treated as a START bit (Figure 10).
Once a start bit has been recognized, the current con-
version must be completed.
DESCRIPTION
SER/DFR
BIT 2
BIT 1
PD1
Digital Output
Data Framing
Serial Clock
BIT 0
PD0
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