LM25007_11 NSC [National Semiconductor], LM25007_11 Datasheet - Page 2

• Manufacturer Part Number: LM25007_11
• Description: Boot Capacitor Regulation in LM25007 Constant-On-Time (COT) Converter
• Manufacturer: NSC [National Semiconductor]

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The Solution
For prebiased startup problem, the source of prebias should
be removed if possible. If the prebias source is some leakage
path in the downstream logic circuit, the system designer
should consider the option of tying unused logic pin, which is
the source of leakage, low. In some cases, this leakage path
may be difficult to identify, or a necessary part of design. In
other cases, the source of prebias may be a stiff source, e.g.,
a battery or super capacitor at the output of the converter. The
system designer can choose from the techniques described
below depending on the constraints of his design.
INCREASING BOOT CAPACITOR (CBST)
The designer can increase the boot capacitor value so that
during no load boot capacitor is not discharged below the gate
threshold of high side switch before V
below the reference. The hiccup free operation should be
verified for whole input voltage (V
RAISING VBST USING EXTERNAL CIRCUIT
If none of the simpler solutions presented above are sufficient,
an external pull up circuit can be used to raise the boot ca-
pacitor voltage (V
switch. An example circuit is shown in
up resistor pulls BST pin up while limiting the current drawn
from V
IN
. The 10V zener prevents the boot capacitor voltage
BST
) above gate threshold (V
FIGURE 4. Raising Boot Capacitor Voltage Using External Circuit
IN
OUT
) range. The designer
Figure
FIGURE 3. Hiccup Mode Operation at No Load
, and hence V
4. The 50kΩ pull
TH
) of high side
FB
, falls
2
should not exceed the recommended boot capacitor value in
the datasheet. This method does not help in case of prebiased
output.
REDUCING FEEDBACK RESISTORS (RFB1, RFB2)
In no load condition, feedback Resistors, FB1 and FB2, con-
stitute the total load at the output of the converter. These
should be chosen so that V
reference level faster than V
(V
input voltage (V
For prebiased outputs during startup, reducing the feedback
resistors effectively pulls the V
thereby raising the boot capacitor (C
of this pull down however depends on the strength and volt-
age level of the prebias source. This method of counteracting
prebias is limited to weak prebias sources or leftover charge
on output capacitor (C
from exceeding the maximum voltage rating between BST
and SW pins. This method is effective for no load as well as
prebiased output conditions. The designer should select the
pull up resistor to optimize the voltage drop across it and the
power dissipation in the pull up resistor and the zener.
TH
). The hiccup free operation should be verified for whole
IN
) range.
OUT
) from previous power cycle.
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OUT
BST
OUT
falls below the gate threshold
and hence V
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and V
BST
) voltage. The extent
SW
closer to ground,
FB
fall below the