HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 39

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3 Interface to Bus Master ..................................................................................................... 512
14.4 Operation........................................................................................................................... 513
14.5 Interrupts ........................................................................................................................... 519
14.6 Usage Notes ...................................................................................................................... 519
Section 15 RAM
15.1 Overview........................................................................................................................... 525
15.2 Register Descriptions ........................................................................................................ 527
15.3 Operation........................................................................................................................... 527
Section 16 ROM
16.1 Overview........................................................................................................................... 529
16.2 Register Descriptions ........................................................................................................ 531
16.3 Operation........................................................................................................................... 532
16.4 PROM Mode ..................................................................................................................... 533
16.5 Programming..................................................................................................................... 536
Section 17 Clock Pulse Generator
17.1 Overview........................................................................................................................... 543
17.2 Register Descriptions ........................................................................................................ 544
17.3 Oscillator........................................................................................................................... 546
14.4.1 Single Mode (SCAN = 0) .................................................................................... 513
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 515
14.4.3 Input Sampling and A/D Conversion Time ......................................................... 517
14.4.4 External Trigger Input Timing ............................................................................. 518
15.1.1 Block Diagram ..................................................................................................... 526
15.1.2 Register Configuration......................................................................................... 526
15.2.1 System Control Register (SYSCR) ...................................................................... 527
16.1.1 Block Diagram ..................................................................................................... 530
16.1.2 Register Configuration......................................................................................... 530
16.2.1 Bus Control Register L (BCRL) .......................................................................... 531
16.4.1 PROM Mode Setting............................................................................................ 533
16.4.2 Socket Adapter and Memory Map ....................................................................... 533
16.5.1 Overview.............................................................................................................. 536
16.5.2 Programming and Verification............................................................................. 536
16.5.3 Programming Precautions .................................................................................... 541
16.5.4 Reliability of Programmed Data .......................................................................... 542
17.1.1 Block Diagram ..................................................................................................... 543
17.1.2 Register Configuration......................................................................................... 544
17.2.1 System Clock Control Register (SCKCR) ........................................................... 544
17.2.2 Low Power Control Register (LPWCR) .............................................................. 545
.................................................................................................................. 525
.................................................................................................................. 529
.................................................................................. 543
Rev.3.00 Mar. 26, 2007 Page xxxix of xlii
REJ09B0355-0300