ADG795A AD [Analog Devices], ADG795A Datasheet - Page 19

• Manufacturer Part Number: ADG795A
• Description: I2C-Compatible, Wide Bandwidth, Five 2:1 Multiplexer
• Manufacturer: AD [Analog Devices]

LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG795A/ADG795G execute all the commands loaded
between two successive write operations that have set the
LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command right after the LDSW bit was
loaded into the device. This setting can be used when the
desired configuration can be achieved by sending a single
command or when the switches and/or GPO pin are not
required to be updated at the same time. When the desired
configuration requires multiple commands with simultaneous
updated, the LDSW bit should be set low while loading the
commands (except the last one when the LDSW bit should be
set high). Once the last command with LDSW = high is loaded,
the device executes all commands received since the last update
simultaneously.
POWER ON/SOFTWARE RESET
The ADG795A/ADG795G has a software reset function
implemented by the RESETB bit from the second data byte
written to the device. For normal operation of the multiplexers
and GPO pin, this bit should be set high. When RESETB = low or
after power-up, the switches from all multiplexers are turned off
(open) and the GPO pin is set low.
Bit Map of the ADG795A
RB15
S1A/D1
Bit Map of the ADG795G
RB15
S1A/D1
Read Operation
SDA
SCL
CONDITION
BY MASTER
START
RB14
S1B/D1
RB14
S1B/D1
ADDRESS BYTE
RB13
S2A/D2
RB13
S2A/D2
A2
RB12
S2B/D2
RB12
S2B/D2
A1
A0
ACKNOWLEDGE
RB11
S3A/D3
RB11
S3A/D3
R/W
BY SWITCH
RB15
RB10
S3B/D3
RB10
S3B/D3
Figure 32. ADG795A/ADG795G Read Operation
RB14
RB13 RB12 RB11 RB10 RB9 RB8
RB9
S4A/D4
RB9
S4A/D4
Rev. 0 | Page 19 of 24
RB8
S4B/D4
RB8
S4B/D4
READ OPERATION
When reading data back from the ADG795A/ADG795G, the
user must begin with an address byte and R/ W bit. The switch
then acknowledges that it is prepared to transmit data by
pulling SDA low. Following this acknowledgement, the
ADG795A/ADG795G transmit two bytes on the next clock
edges. These bytes contain the status of the switches, and each
byte is followed by an acknowledge bit. A logic high bit
represents a switch in the on (close) state while a low represents
a switch in the off (open) state. For the GPO pin (ADG795G
only), the bit represents the logic value of the pin. Figure 32
illustrates the entire read sequence.
The bit maps accompanying Figure 32 show the relationship
between the elements of the ADG795A and ADG795G (that it,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.
RB7
S5A/D5
RB7
S5A/D5
ACKNOWLEDGE
BY SWITCH
RB6
S5B/D5
RB6
S5B/D5
RB7
RB6
RB5
RB5
-
RB5
-
RB4
RB4
-
RB4
-
RB3 RB2 RB1 RB0
ADG795A/ADG795G
RB3
GPO1
RB3
-
ACKNOWLEDGE
RB2
-
RB2
-
BY SWITCH
CONDITION
BY MASTER
RB1
-
RB1
-
STOP
RB0
-
RB0
-