LM4681SQ NSC [National Semiconductor], LM4681SQ Datasheet - Page 14

• Manufacturer Part Number: LM4681SQ
• Description: 10 Watt Stereo CLASS D Audio Power Amplifier with Stereo Headphone Amplifier and I2C/SPI Volume Control
• Manufacturer: NSC [National Semiconductor]

www.national.com
General Features
Thermal Protection
The LM4681 has thermal shutdown circuitry that monitors
the die temperature. Once the LM4681 die temperature
reaches 170˚C, the LM4681 disables the output switching
waveform and remains disabled until the die temperature
falls below 140˚C (typ).
Over-Modulation Protection
The LM4681’s over-modulation protection is a result of the
preamplifier’s (AMP1 and AMP2, Figure 1) inability to pro-
duce signal magnitudes that equal the power supply volt-
ages. Since the preamplifier’s output magnitude will always
be less than the supply voltage, the duty cycle of the ampli-
fier’s switching output will never reach zero. Peak modula-
tion is limited to a nominal 95%.
I
The LM4681 uses a serial bus, which conforms to the I
protocol, to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I
this discussion, the master is the controlling microcontroller
and the slave is the LM4681.
The I
ADR pin. The LM4681’s two possible I
of the form 110110X
low, and X
used to address a number of chips in a system, the
LM4681’s chip address can be changed to avoid possible
address conflicts.
The bus format for the I
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
dress against their own address.
2
C Compatible Interface
2
C address for the LM4681 is determined using the
1
= 1, if ADR is a logic high. If the I
1
0 (binary), where X
2
C interface is shown in Figure 5. The
2
C bus to check the incoming ad-
(Continued)
2
C standard is 400kHz. In
2
C chip addresses are
1
= 0, if ADR is logic
2
C interface is
2
C
14
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master
releases the data line high (through a pull-up resistor). Then
the master sends an acknowledge clock pulse. If the
LM4681 has received the address correctly, then it holds the
data line low during the clock pulse. If the data line is not
held low during the acknowledge clock pulse, then the mas-
ter should abort the rest of the data transfer to the LM4681.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4681 received the data.
If the master has more data bytes to send to the LM4681,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
SPI Interface
The LM4681’s serial control interface is compatible with SPI
signals and protocols. When using SPI signals, the ADR pin
is the input for the SPI ENABLE signal, the SDA pin is the
input for the SPI CLOCK signal, and the SDA pin is the SPI
DATA input.
I
The LM4681’s I
I
a voltage level set by the I
independent to that of the main power supply pin V
is ideal whenever logic levels for the I
dictated by a microcontroller or microprocessor that is oper-
ating at a lower supply voltage than the main battery of a
portable system.
2
2
C/SPI Interface Power Supply Pin (I
C/SPI V
DD
pin. The LM4681’s I
2
C/SPI interface is powered up through the
2
C/SPI V
2
C/SPI interface operates at
DD
pin which can be set
2
2
C/SPI interface are
C V
DD
)
DD
. This