74AC175_07 FAIRCHILD [Fairchild Semiconductor], 74AC175_07 Datasheet

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74AC175_07

Manufacturer Part Number
74AC175_07
Description
Quad D-Type Flip-Flop
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
FACT™ is a trademark of Fairchild Semiconductor Corporation.
74AC175, 74ACT175
Quad D-Type Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
74AC175SC
74AC175SJ
74AC175MTC
74AC175PC
74ACT175SC
74ACT175SJ
74ACT175MTC
I
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
Asynchronous common reset
True and complement output
Outputs source/sink 24mA
ACT175 has TTL-compatible inputs
CC
Number
Order
reduced by 50%
Package
Number
MTC16
MTC16
M16A
M16D
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop.
The device is useful for general flip-flop requirements
where clock and clear inputs are common. The informa-
tion on the D-type inputs is stored during the LOW-to-
HIGH clock transition. Both true and complemented out-
puts of each flip-flop are provided. A Master Reset input
resets all flip-flops, independent of the Clock or D-type
inputs, when LOW.
Pin Descriptions
Package Description
MR
Q
Q
D
CP
Pin Names
0
0
0
–Q
–Q
–D
3
3
3
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
Description
www.fairchildsemi.com
April 2007
tm

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74AC175_07 Summary of contents

Page 1

Quad D-Type Flip-Flop Features ■ I reduced by 50% CC ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Asynchronous common reset ■ True and complement output ■ Outputs source/sink 24mA ■ ACT175 has TTL-compatible inputs Ordering ...

Page 2

Logic Symbol IEEE/IEC Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 Functional Description The AC/ACT175 ...

Page 3

Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...

Page 4

DC Electrical Characteristics for AC Symbol Parameter V Minimum HIGH Level IH Input Voltage V Maximum LOW Level IL Input Voltage V Minimum HIGH Level OH Output Voltage V Maximum LOW Level OL Output Voltage (3) I Maximum Input IN ...

Page 5

DC Electrical Characteristics for ACT Symbol Parameter V Minimum HIGH Level IH Input Voltage V Maximum LOW Level IL Input Voltage V Minimum HIGH Level OH Output Voltage V Maximum LOW Level OL Output Voltage I Maximum Input IN Leakage ...

Page 6

AC Electrical Characteristics for AC Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay, PLH Propagation Delay, PHL Propagation Delay, t PLH MR to ...

Page 7

AC Electrical Characteristics for ACT Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay, PLH Propagation Delay, PHL Propagation Delay, PLH MR to ...

Page 8

Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 Package Number M16A 8 www.fairchildsemi.com ...

Page 9

Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 Package Number M16D 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.00±0.10 4.55 0.11 MTC16rev4 Figure 4. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 0.65 4.4±0.1 1.45 Package Number ...

Page 11

Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 5. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 Package Number N16E 11 www.fairchildsemi.com ...

Page 12

TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build ...

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