74LCXZ16244GX FAIRCHILD [Fairchild Semiconductor], 74LCXZ16244GX Datasheet

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74LCXZ16244GX

Manufacturer Part Number
74LCXZ16244GX
Description
Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
© 2001 Fairchild Semiconductor Corporation
74LCXZ16244GX
(Note 1)
74LCXZ16244MEA
(Note 2)
74LCXZ16244MTD
(Note 2)
74LCXZ16244
Low Voltage 16-Bit Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
General Description
The LCXZ16244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
When V
high impedance state during power up or power down. This
places the outputs in high impedance (Z) state preventing
intermittent low impedance loading or glitching in bus ori-
ented applications.
The LCXZ16244 is designed for low voltage (2.7V or 3.3V)
V
environment.
The LCXZ16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
CC
Order Number
applications with capability of interfacing to a 5V signal
CC
is between 0 and 1.5V, the LCXZ12644 is in the
Package Number
(Preliminary)
BGA54A
MS48A
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500252
Features
I 5V tolerant inputs and outputs
I Guaranteed power up/down high impedance
I Supports live insertion/withdrawal
I 2.7V–3.6V V
I 4.5 ns t
I ± 24 mA output drive (V
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
I Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Human body model > 2000V
Machine model > 200V
Package Description
PD
max (V
CC
specifications provided
CC
= 3.0V), 20 µ A I
CC
= 3.0V)
September 2000
Revised August 2001
CC
www.fairchildsemi.com
max

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74LCXZ16244GX Summary of contents

Page 1

... The LCXZ16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing CMOS low power dissipation. Ordering Code: Order Number Package Number 74LCXZ16244GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1) (Preliminary) [TAPE and REEL] ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Inputs –O Outputs ...

Page 3

Functional Description The LCXZ16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 5

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Data to Output PLH t Output Enable Time PZL t PZH t Output Disable Time PLZ t PHZ t Output to Output Skew (Note 7) OSHL t OSLH Note 7: ...

Page 6

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C 6V for V Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics ...

Page 7

Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A Preliminary 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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