MAX849 MAXIM [Maxim Integrated Products], MAX849 Datasheet - Page 11

• Manufacturer Part Number: MAX849
• Description: 1-Cell to 3-Cell, High-Power, Low-Noise, Step-Up DC-DC Converters
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 4. Controller Block Diagram in PWM Mode
where V
age, and V
good comparator.
The MAX848/MAX849 feature a power-good compara-
tor. This comparator’s open-drain output, POK, is
pulled low when the output voltage falls below the nom-
inal internal threshold level of 3V with POKIN = 0V. To
set the power-good trip level externally, refer to the
Setting the Output Voltage Externally section.
The MAX848/MAX849 have an internal, two-channel, seri-
al ADC. The ADC converts an analog input voltage into a
digital stream available at the DATA pin. The converter
skips clock pulses in proportion to the input voltage.
Output format is a return-to-zero bit stream with a bit
duration of 1/f
are skipped and DATA remains low; with a positive full-
scale input voltage, no pulses are skipped; and at mid-
scale, every other pulse is skipped. The ADC’s clock is
one-half of the externally applied clock signal or one-half
of the internal 300kHz clock available at LX. In PFM
mode, the converter is not active and DATA is driven low.
Channel 1, AIN1, has an input voltage range of 0.625V
to 1.875V and is selected when AINSEL is low. Channel
2, AIN2, accepts inputs in the 0V to 2.5V range and is
selected when AINSEL is pulled high (Figure 6).
The ADC is a switched-capacitor type; therefore, an
anti-aliasing filter might be required at the inputs. Insert
a 1kΩ series resistor and a 0.01µF filter capacitor in
noisy environments.
PWM-MODE
LIMIT LEVEL
FEEDBACK
CURRENT-
REF
OSC
REF
TRIP
Analog-to-Digital Converter (ADC)
= 1.25V, V
CLK
is the desired trip level for the power-
. At zero-scale input voltage, all pulses
______________________________________________________________________________________
Low-Noise, Step-Up DC-DC Converters
OUT
S
R
is the desired output volt-
Q
Power-OK
P
N
1-Cell to 3-Cell, High-Power,
PGND
LX
POUT
Implement the necessary counter functions either with
discrete hardware or with microcontroller (µC) imple-
mentations. The output resolution depends on how
many of the ADC clock pulses are counted, as shown
in Figure 7.
A complete hardware solution can be implemented
using either two counters or an ASIC. Resolution
depends on how many pulses are counted. The main
advantage of the discrete hardware implementation is
that accuracy is not affected by interrupt latency asso-
ciated with the µC solution.
Figure 5. Adjustable Output Voltage and Power-Good Trip Level
Figure 6. A/D Converter Block Diagram
AINSEL
2 x REF
AIN1
AIN2
OSC
C/2
C/2
GND
C
2
MAX848
MAX849
POK
POKIN
REF
Timer Function Implementation
OUT
FB
C
Hardware Implementation
D
R2
R3
R1
Q
OUTPUT
DATA
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