DM74LS502N NSC [National Semiconductor], DM74LS502N Datasheet - Page 3

• Manufacturer Part Number: DM74LS502N
• Description: 8-Bit Successive Approximation Register
• Manufacturer: NSC [National Semiconductor]

Figure a shows a simplified hook-up of a LS502 a D A con-
Switching Characteristics
Functional Description
The register stages are composed of transparent RS latch-
es arranged in master slave pairs The master and slave
latches are enabled separately by non-overlapping comple-
mentary signals
input Master latches are enabled when CP is LOW and
slave latches are enabled when CP is HIGH Information is
transferred from master to slave and thus to the outputs by
the LOW-to-HIGH transition of CP
Initializing the register requires a LOW signal on S while
exercising CP With S and CP LOW all master latches are
SET (Q side HIGH) A LOW-to-HIGH CP transition with S
remaining LOW then forces the slave latches to the condi-
tion wherein Q7 is LOW and all other register outputs in-
cluding CC are HIGH This condition will prevail as long as
S remains LOW regardless of subsequent CP rising edge
To start the conversion process S must return to the HIGH
state On the next CP rising edge the information stored in
the serial data input latch is transferred to Q
Q6 is forced to the LOW state On the rising edge of the
next seven clocks this LOW signal is shifted downstream
one bit at a time while the serial data enters the register
position one bit behind this LOW signal as shown in the
Truth Table Note that after a serial data bit appears at a
particular output that register position undergoes no further
changes After the shifted LOW signal reaches CC the reg-
ister is locked up and no further changes can occur until the
register is initialized for the next conversion process
verter and a comparator arranged to convert an analog in-
put voltage into an 8-bit binary number by the successive
approximation technique Figure b is an idealized graph
showing the various values that the D A converter output
voltage can assume in the course of the conversion The
vertical axis is calibrated in fractions of the full-scale output
capability of the D A converter and the horizontal axis rep-
resents the successive states of the Truth Table At time t1
Q7 is LOW and Q6–Q0 are HIGH causing the D A output
to be one-half of full scale If the analog input voltage is
greater than this voltage the comparator output (hence the
D input of the LS502) will be LOW and at times t2 the D A
output will rise to three-fourths of full scale because Q7 will
remain LOW and contribute 50% while Q6 is forced LOW
and contributes another 25% On the other hand if the ana-
log input voltage is less than one-half of full scale the com-
parator output will be HIGH and Q7 will go HIGH at t2 Q6
will still be forced LOW at t2 and the D A output will de-
crease to 25% of full scale Thus with each successive
clock the D A output will change by smaller increments
When the conversion is completed at t9 the binary number
represented by the register outputs will be the numerator of
the fraction n 256 representing the analog input voltage as
a fraction of the full scale output D A converter
Symbol
f
t
t
max
PLH
PHL
Maximum Clock Frequency
Propagation Delay
CP to Q
1 and
n
Parameter
or CC
2 derived internally from the CP
V
D
CC
and Q7 while
e a
5 0V T
Min
25
DM54LS502
A
e a
3
25 C
R
Max
L
35
25
e
2 k
C
L
e
15 pF
Min
15
FIGURE b
FIGURE a
DM74LS502
Max
35
25
TL F 10189– 4
TL F 10189– 5
Units
MHz
ns