AT93C46B-10PC-2.5 ATMEL [ATMEL Corporation], AT93C46B-10PC-2.5 Datasheet
AT93C46B-10PC-2.5
Related parts for AT93C46B-10PC-2.5
AT93C46B-10PC-2.5 Summary of contents
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... ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C46B is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions. Pin Configuration Pin Name Function ...
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... Storage Temperature............................- +150 C Voltage on Any Pin with Respect to Ground........................... -1.0V to +7.0V Maximum Operating Voltage .................................6.25V DC Output Current ..............................................5.0 mA Block Diagram AT93C46B 2 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and ...
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Pin Capacitance Applicable over recommended operating range from T Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended ...
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... CS Hold Time CSH t DI Hold Time DIH t Output Delay to ‘1’ PD1 t Output Delay to ‘0’ PD0 Status Valid High Impedance DF t Write Cycle Time WP Endurance AT93C46B 4 = -40° 85° +2. 5.5V Test Condition 4.5V V 5.5V CC 2.7V V 5.5V CC 2.5V V 5. ...
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... Instruction Set for the AT93C46B Instruction SB Op Code READ 1 EWEN 1 ERASE 1 WRITE 1 ERAL 1 WRAL 1 EWDS 1 Address (x16) Comments Reads data stored in memory, at specified address 11XXXX Write enable must precede all programming modes Erase memory location Writes memory location A ...
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... Functional Description The AT93C46B is accessed via a simple and versatile three-wire serial communication interface. Device opera- tion is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic ‘1’) followed by the appro- priate Op Code and the desired memory Address location ...
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... Organization Key for Timing Diagrams I READ Timing EWEN Timing (1) EWDS Timing Note: 1. Requires a minimum of nine clock cycles. AT93C46B (x16 ...
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... WRITE Timing (1)(2) WRAL Timing Notes: 1. Valid only 4.5V to 5.5V Requires a minimum of nine clock cycles. ERASE Timing AT93C46B 8 ...
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TERAL Timing Note: 1. Valid only 4.5V to 5.5V ...
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... Standard Device (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -2.5 Low Voltage (2.5V to 5.5V) AT93C46B 10 I (max MAX ( A) (kHz) Ordering Code AT93C46B-10PC 50.0 2000 AT93C46B-10SC AT93C46B-10PC-2.7 20.0 1000 AT93C46B-10SC-2.7 AT93C46B-10PC-2.5 20.0 500 AT93C46B-10SC-2.5 AT93C46B-10PI 50.0 2000 AT93C46B-10SI AT93C46B-10PI-2.7 20.0 1000 AT93C46B-10SI-2.7 AT93C46B-10PI-2.5 20.0 500 AT93C46B-10SI-2.5 Package Type Options Package Operation Range 8P3 Commercial 8S1 ...