AT93C56A-W1.8-11 ATMEL [ATMEL Corporation], AT93C56A-W1.8-11 Datasheet
AT93C56A-W1.8-11
Related parts for AT93C56A-W1.8-11
AT93C56A-W1.8-11 Summary of contents
Page 1
... EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3) packages. The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO ...
Page 2
... When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. AT93C56A/66A 2 *NOTICE: Stresses beyond those listed under “ ...
Page 3
Table 2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: 1. This parameter is characterized and is not 100% tested. Table 3. ...
Page 4
... Output Delay to “0” PD0 Status Valid High t DF Impedance t Write Cycle Time WP (1) Endurance 5.0V, 25°C Note: 1. This parameter is characterized and is not 100% tested. AT93C56A/66A 4 = − 40° 85° Test Condition 4.5V ≤ V ≤ 5.5V CC 2.7V ≤ V ≤ 5.5V CC 1.8V ≤ V ≤ 5.5V CC 2.7V ≤ V ≤ ...
Page 5
... DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A supports sequential read operations. The device will automatically increment the inter- nal address pointer and clock out the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (logic “ ...
Page 6
... Timing Diagrams Figure 2. Synchronous Data Timing Note: 1. This is the minimum SK period. AT93C56A/66A 6 WRITE (WRITE): The Write (WRITE) instruction contains the bits of data to be written into the specified memory location. The self-timed programming cycle t after the last bit of data is received at serial data input pin DI. The DO pin outputs the ...
Page 7
... SK DI High Impedance DO Figure 4. EWEN Timing Figure 5. EWDS Timing 3378K–SEEPR–12/06 Table 6. Organization Key for Timing Diagrams AT93C56A (2K Notes DON’T CARE value, but the extra clock is required DON’ ...
Page 8
... Figure 6. WRITE Timing HIGH IMPEDANCE DO (1) Figure 7. WRAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC Figure 8. ERASE Timing HIGH IMPEDANCE DO AT93C56A/66A 8 ... ... ... ... N-1 N BUSY READY ...
Page 9
Figure 9. ERAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC 3378K–SEEPR–12/ STANDBY CHECK STATUS BUSY HIGH IMPEDANCE ...
Page 10
... AT93C56AY1-10YU-1.8 (Not recommended for new design) (3) AT93C56AY6-10YH-1.8 (4) AT93C56A-W1.8-11 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green package + RoHS compliant. 3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing ...
Page 11
AT93C66A Ordering Information Ordering Code (2) AT93C66A-10PU-2.7 (2) AT93C66A-10PU-1.8 (2) AT93C66A-10SU-2.7 (2) AT93C66A-10SU-1.8 (2) AT93C66AW-10SU-2.7 (2) AT93C66AW-10SU-1.8 (2) AT93C66A-10TU-2.7 (2) AT93C66A-10TU-1.8 (2) AT93C66AU3-10UU-1.8 (2) AT93C66AY1-10YU-1.8 (Not recommended for new design) (3) AT93C66AY6-10YH-1.8 (4) AT93C66A-W1.8-11 Notes: 1. For 2.7V devices used ...
Page 12
... E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R AT93C56A/66A ...
Page 13
JEDEC SOIC e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 3378K–SEEPR–12/06 1 ...
Page 14
... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/ 0.005 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT93C56A/66A End View b ...
Page 15
MAP D E Top View Side View 2325 Orchard Parkway San Jose, CA 95131 R 3378K–SEEPR–12/ End View A SYMBOL TITLE 8Y1, 8-lead (4.90 x 3.00 mm ...
Page 16
... Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 2325 Orchard Parkway San Jose, CA 95131 R AT93C56A/66A 16 A Pin 1 Index ...
Page 17
TSSOP Pin 1 indicator this corner N Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, ...
Page 18
... Bottom View 8 Solder Balls 1. This drawing is for general information only. 2. Dimension ‘b’ is measured at maximum solder ball diameter 1150E Cheyenne Mt. Blvd Colorado Springs, CO 80906 R AT93C56A/66A TITLE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) 1 ...
Page 19
Revision History 3378K–SEEPR–12/06 Revision No. Date Comments 3378K 12/06 Removed DC/Don’t Connect and replaced with NC/No Conenct Adjusted size of Block diagram on pg. 2 Made all diagrams on pages 6-9 consistently the same size Corrected 8U3-1 19 ...
Page 20
... Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...