AT25128A ATMEL [ATMEL Corporation], AT25128A Datasheet
AT25128A
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AT25128A Summary of contents
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... The devices are available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages. The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK) ...
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... Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA AT25128A/256A 2 Block write protection is enabled by programming the status register with top one-forth, top one-half, or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protec- tion is provided via the WP pin to protect against inadvertent write attempts to the status register ...
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... 3.6 ≤ V ≤ ≤ 3.6V 2.7≤ 0.15mA CC OL 3.6 ≤ V ≤ 5.5V = −1 ≤ 3.6V = −100 mA 2.7≤ AT25128A/256A = +5.0V (unless otherwise noted) CC Max Units +2.7V to +5.5V CC Min Typ Max 2.7 5.5 4.5 5.5 2.0 3.0 3.0 5.0 3.5 6.0 (1) 0.5 12.0 (1) 2.0 15.0 −3.0 3.0 −3.0 3.0 − ...
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... Hold to Output High Output Disable Time DIS t Write Cycle Time WC (1) Endurance 5.0V, 25°C, Page Mode Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. AT25128A/256A 4 = −40°C to +125° Specified Voltage Min 2.7–5.5 0 2.7–5.5 2.7–5.5 2.7–5.5 40 2.7– ...
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... WPEN bit in the status register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “ ...
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... AT25128A/256A 6 Figure 2. SPI Serial Interface AT25128A/256A 5088C–SEEPR–11/04 ...
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... Bit 7 (WPEN) See Table 9. Bits 0–7 are “1”s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128A/256A is divided into four array segments. AT25128A/256A Operation Set Write Enable Latch ...
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... X High 1 READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed by the byte address to be read (see Table 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the spec- ified address is then shifted out onto the SO line ...
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... Only the RDSR instruction is enabled during the write pro- gramming cycle. The AT25128A/256A is capable of a 64-byte page write operation. After each byte of data is received, the six low-order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten ...
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... Timing Diagrams (for SPI Mode 0 [0, 0]) Figure 3. Synchronous Data Timing CSS V IH SCK HI Figure 4. WREN Timing Figure 5. WRDI Timing AT25128A/256A VALID CSH t t DIS HO HI-Z 5088C–SEEPR–11/04 ...
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... Figure 6. RDSR Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO Figure 7. WRSR Timing 5088C–SEEPR–11/ MSB AT25128A/256A DATA OUT ...
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... Figure 8. READ Timing Figure 9. WRITE Timing Figure 10. HOLD Timing CS SCK HOLD SO AT25128A/256A 5088C–SEEPR–11/04 ...
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... AT25128A Ordering Information Ordering Code AT25128A-10PE-2.7 AT25128AN-10SE-2.7 AT25128A-10PQ-2.7 AT25128AN-10SQ-2.7 AT25128A-10TQ-2.7 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) − ...
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... Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) −2.7 Low-voltage (2.7V to 5.5V) AT25128A/256A 14 Package 8P3 8S1 8P3 8S1 8A2 Package Type ...
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... Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R 5088C–SEEPR–11/ TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) AT25128A/256A End View COMMON DIMENSIONS (Unit of Measure = inches) MIN MAX SYMBOL NOM A – – 0.210 A2 ...
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... JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25128A/256A TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...
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... Dimension D and determined at Datum Plane H. 2325 Orchard Parkway San Jose, CA 95131 R 5088C–SEEPR–11/ TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) AT25128A/256A L1 L End View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL D 2.90 3.00 3 ...
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... Atmel Corporation 2004. All rights reserved. Atmel is a trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...