AT88SA102S_11 ATMEL [ATMEL Corporation], AT88SA102S_11 Datasheet - Page 11

• Manufacturer Part Number: AT88SA102S_11
• Description: Atmel CryptoAuthentication Product Authentication Chip
• Manufacturer: ATMEL [ATMEL Corporation]

5.1.3
5.1.4
5.2
5.3
Sleep Flag
The sleep flag is used to transition AT88SA102S to the low power state, which causes a complete reset of the AT88SA102S
internal command engine and input/output buffer. It can be sent to AT88SA102S at any time when AT88SA102S will accept a
flag.
To achieve the specified I
achieve I
additional leakage on the input circuit of the chip.
The system must calculate the total time required for all commands to be sent to AT88SA102S during a single session,
including any inter-bit/byte delays. If this total time exceeds t
then a Sleep flag, then a Wake token, and finally after the Wake delay the remaining commands.
Pause State
The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has expired and the
chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the signal pin but does not enter a
low power consumption mode.
The pause state provides a mechanism for multiple AT88SA102S chips on the same wire to be selected and to exchange data
with the host microprocessor. The PauseLong command includes an optional address field which is compared to the values in
Fuses 84-87. If the two matches, then the chip enter the pause state, otherwise it continues to monitor the bus for subsequent
commands. The host would selectively put all but one AT88SA102S’ in the pause state before executing the MAC command
on the active chip. After the end of the watchdog interval all the chips will have entered the sleep state and the selection
process can be started with a Wake token (which will then be honored by all chips) and selection of a subsequent chip.
IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way:
The general IO flow for the MAC command is as follows:
All commands other than MAC have a short execution delay. In these cases, the system should omit steps six, seven, and
eight and replace this with a wait of duration t
Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and AT88SA102S will fall out of
synchronization with each other. In order to speed recovery, AT88SA102S implements a timeout that forces the chip to sleep.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Receive output block from the AT88SA102S, system checks CRC
11. If CRC from the AT88SA102S is incorrect, indicating a transmission error, system resends transmit flag
12. System sends sleep flag to the AT88SA102S
System sends Wake token
System sends Transmit flag
Receive 0x11 value from the AT88SA102S to verify proper wakeup synchronization
System sends command flag
System sends complete command block
System waits t
System sends Transmit flag. If command format is OK, the AT88SA102S ignores this flag because the computation
System waits t
System sends transmit flag
engine is busy. If there was an error, the AT88SA102S responds with an error code
SLEEP
if the sleep state of the input pin is high, the voltage on the input signal should be within 0.3 V of V
PARSE
EXEC
SLEEP
, see Section 5.1.1
for the AT88SA102S to check for command formation errors
, Atmel recommends that the input signal be brought below V
PARSE
+ t
EXEC
.
WATCHDOG
then the system must issue a partial set of commands,
Atmel AT88SA102S [DATASHEET]
IL
when the chip is asleep. To
8584G−CRYPTO−9/11
CC
to avoid
11