AT88SC0104CA_11 ATMEL [ATMEL Corporation], AT88SC0104CA_11 Datasheet - Page 19

• Manufacturer Part Number: AT88SC0104CA_11
• Description: Atmel CryptoMemory Specification Datasheet
• Manufacturer: ATMEL [ATMEL Corporation]

6.3.8
6.3.8.1 SME – Supervisor Mode Enable
6.3.8.2 UCR – Unlimited Checksum Reads
6.3.8.3 UAT – Unlimited Authentication Trials
6.3.8.4 ETA – Eight Trials Allowed
6.3.8.5 CS0 – CS3: Programmable Chip Select (Only Relevant in Synchronous Protocol)
6.3.9
Device Configuration Register (DCR)
This 8-bit register allows selection of the following device configuration options (active low). The values programmed have an
immediate effect on the logic of the device. The default value is “1” for each bit.
Table 6-4.
Asserting this bit (SME = “0”) enables supervisor mode for Write 7 password such that verifying Write 7 password grants read
and write accesses to all password sets and PACs. Verifying Write 7 password does not grant access to other passwords
when this bit is not asserted (SME = “1”).
Asserting this bit (UCR = “0”) allows unlimited number of checksum reads without requiring a new authentication. Not asserting
this bit (UCR = “1”) limits the read of checksum to one attempt after which the device resets the crypto algorithm after
executing the read checksum command.
Asserting this bit (UAT = “0”) disables the Authentication Attempts Counter (AAC) thus allowing unlimited authentication
attempts. The AAC decrements after each unsuccessful attempt but the internal logic ignores it value. Asserting this bit also
prevents reset of the crypto algorithm after reading the MAC in encryption mode. The UAT bit does not affect the password
attempts counter.
Asserting this bit (ETA = “0”) extends the trials limit to 8 incorrect attempts to authenticate or verify a password. The counter
(AAC or PAC) will decrement ($FF, $FE, $FC, $F8, $F0, $E0, $C0, $80, $00) with each incorrect attempt. Disabling this bit
(ETA = “1”) limits authentication and password verification trials to only four incorrect attempts ($FF, $EE, $CC, $88, $00).
The four most significant bits (b4 – b7) of every command comprise the chip select address. All CryptoMemory devices will
respond to the default chip select address of $B (1011). Each device also responds to a second chip select address
programmed into CS0-CS3 of the device configuration register. By programming each device to a unique chip select address,
it is possible to connect up to 15 devices on the same serial data bus and communicate individually to each. Global
communications to all devices sharing the bus is accomplished using the default chip select address $B.
Access Registers
Four (AT88SC0104CA/0204CA/0404CA) or eight (AT88SC0808CA) 8-bit access registers allow personalization of the device.
Each access register works in conjunction with a password/key register to define the security settings for each individual zone
of the user memory. Values in the access registers take immediate effect after programming. The default value for each bit is
“1”.
Table 6-5.
Bit 7
SME
Bit 7
PM1
Device Configuration Register (DCR)
Access Register
Bit 6
UCR
Bit 6
PM0
Bit 5
Bit 5
UAT
AM1
Atmel AT88SC0104CA/0204CA/0404CA/0808CA [Datasheet]
Bit 4
Bit 4
AM0
ETA
Bit 3
Bit 3
CS3
ER
WLM
Bit 2
Bit 2
CS2
Bit 1
Bit 1
MDF
CS1
8664E−CRYPTO−12/11
Bit 0
Bit 0
PGO
CS0
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