AT49LL080-33JC ATMEL [ATMEL Corporation], AT49LL080-33JC Datasheet
AT49LL080-33JC
Related parts for AT49LL080-33JC
AT49LL080-33JC Summary of contents
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... Industry-standard Package – 40-lead TSOP or 32-lead PLCC Description The AT49LL080 is a Flash memory device designed to interface with the LPC bus for PC Applications. A feature of the AT49LL080 is the nonvolatile memory core. The high-performance memory is arranged in sixteen sectors (see page 11). The AT49LL080 supports two hardware interfaces: Low Pin Count (LPC) for in-system operation and Address/Address Multiplexed (A/A Mux) for programming during manu- facturing ...
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... A/A Mux) and internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation. Specifically designed for 3V systems, the AT49LL080 supports read operations at 3.3V and sector erase and program operations at 3.3V and 12V V ders the fastest program performance which will increase factory throughput, but is not recommended for standard in-system LPC operation in the platform ...
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... Since this pin is internally pulled down and thus can be left unconnected, the AT49LL080 is compatible with systems that do not use a CE signal. To reduce power, the device is placed in a low-power standby mode when CE is high. ...
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... SUPPLY X V SUPPLY X CCa AT49LL080 4 A/A Mux Name and Function GENERAL PURPOSE INPUTS: These individual inputs can be used for additional board flexibility. The state of these pins can be read through LPC registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain at the same level until the end of the read cycle ...
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... LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. RESET: RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low deselects the memory, places output drivers in a high-impedance state, and turns off all AT49LL080 . IL Description ...
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... LPC memory may be providing status information instead of memory array data). CYCLE TYPES: There are two types of cycles that are supported by the AT49LL080: LPC Memory Read and LPC Memory Write. READ: Read operations consist of START, CYCTYPE + DIR, ADDRESS, TAR, SYNC and data fields as shown in Figure 1 and described in Table 5 ...
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... MADDR (MEMORY ADDRESS): This is an eight-clock field, which gives a 32-bit mem- ory address. LPC supports the 32-bit address protocol. The address is transferred with the most significant nibble first. For the AT49LL080, address bit 23 directs Reads and Writes to memory locations ( register access locations (A ...
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... CYCTYPE + DIR ADDR 11 TAR0 12 TAR1 WSYNC 15 RSYNC 16 DATA 17 DATA 18 TAR0 19 TAR1 Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LL080 ADDR TAR SYNC(3) (1) Field Contents LAD[3:0] LAD[3:0] Direction 0000b IN 010xb IN YYYY IN ...
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... Flash command. 1111b OUT The LPC Flash memory drives LAD0 - LAD3 to 1111b to indicate then Float a turnaround cycle. Float then The LPC Flash memory floats its outputs, the master (ICH) takes IN control of LAD3 - LAD0. AT49LL080 TAR SYNC TAR 9 ...
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... Bus Abort AT49LL080 10 OUTPUT DISABLE: When the LPC is not selected through a LPC read or write cycle, the LPC interface outputs (LAD[3:0]) are disabled and will be placed in a high-imped- ance state. The Bus Abort operation can be used to immediately abort the current bus operation. A ...
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... A series of registers are available in the LPC to provide software read and write locking and GPI feedback. These registers are accessible through standard addressable mem- ory space. REGISTERS: The AT49LL080 has two types of registers: sector-locking registers and general-purpose input registers. The two types of registers appear at their respective address locations in the 4 GB system memory map. ...
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... Table 7. Sector-locking Registers for AT49LL080 Register Name Sector Size LR15 64K LR14 64K LR13 64K LR12 64K LR11 64K LR10 64K LR9 64K LR8 64K LR7 64K LR6 64K LR5 64K LR4 64K LR3 64K LR2 64K LR1 64K LR0 64K FGPI-REG Table 8 ...
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... GPI[4:0] pins on the LPC at power-up. Since this is a pass-through register, there is no default value as shown in Table recommended that the GPI pins be in the desired state before LFRAME is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. AT49LL080 (1) Resulting Sector State Full access Write locked – ...
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... Either 40H or 10H is recognized as the program setup. 5. Following the Product ID Entry command, read operations access manufacture and device ID. See Table 11. 6. AID = Address used to read data for manufacture or device ID. 7. SRD = Data Read from status register. AT49LL080 14 1st Bus Cycle Operation ...
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... SECTOR ERASE: Before a byte can be programmed, it must be erased. The erased state of the memory bits is a logical “1”. Since the AT49LL080 does not offer a complete chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. ...
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... AT49LL080 16 sector erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the sector erase suspend command is written. Poll- ing the status register can help determine when the sector erase operation was suspended. After a successful suspend, a Read Array command can be written to read data from a sector other than the suspended sector ...
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... The AT49LL080 is designed to offer a parallel programming mode for faster factory pro- gramming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The IC pin is pulled down internally in the AT49LL080 modest current should be expected to be drawn (see Table 1 on page 3 for further information). Four control pins dictate data flow in and out of the component: R/C, OE, WE, and RST ...
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... AT49LL080 18 BUS OPERATION: All A/A Mux bus cycles can be conformed to operate on most auto- mated test equipment and PROM programmers. Bus Operations Mode RST OE (1)(5) Read (5) Output Disable (5) Product ID Entry (3)(4)(5) Write Notes can for control and address input pins and V ...
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... OUT I = 1500 µA OUT AT49LL080 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
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... All currents are in RMS unless otherwise noted. These currents are valid for all packages 0 0 This number is the worst case of I AT49LL080 20 Conditions (2) Voltage range of all inputs LFRAME = 3.6V, CC CLK MHz No internal operations in ...
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... IN CC (1) 0 0.6 V load CC CC (1) 0 0.2 V load *( OUT OUT Condition peak-to-peak t CYC t HIGH 0 0.2 V AT49LL080 Min Max - -17 OUT Note 2 - -17 OUT Note - 1)/0.015 1)/0.015 Min ...
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... For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. This parameter applies to any input type (excluding CLK). Output Timing Parameters (Valid Output Data) (Float Output Data) Input Timing Parameters LAD[3:0] (Valid Input Data) AT49LL080 22 (1) (2) (2) (3) (3) (2) CLK ...
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... V CC specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production t PLPH 3. (1) Typ Max 30.0 300 2.0 20.0 0.8 1.0 = +25 C and nominal voltages. A AT49LL080 Value V/ns and V . Timing parameters must be met with no more IH IL Min Max , this ...
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... V IH RST V IL AT49LL080 24 ELECTRICAL CHARACTERISTICS IN A/A MUX MODE: Certain specifications differ from the previous sections, when programming in A/A Mux Mode. The following subsec- tions provide this data. Any information that is not shown here is not specific to A/A Mux Mode and uses the LPC Mode specifications. ...
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... R/C without impact on t CHQV GLQV . CC t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV High-Z t GLQX AT49LL080 Min Max 250 150 CHQV Next Address Stable t GLQV t GHQZ t QXGH ...
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... WE High to RY/BY Going Low WHRL t V Hold from Valid SRD, RY/BY High QVVL PP1,2 Notes: 1. Refer to “A/A Mux Read-only Operations” for valid +85 C, 3.3V ± 0. AT49LL080 26 (1) (1) (1) (1) (1) and D for sector erase or program, or other commands Min ...
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... C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command 3273C–FLASH–5/ AVCH t CLAX t t PHWL WHWL t WLWH t WHDX t DVWH VPWH AT49LL080 CHAX t CHWH t WHGL Valid IN SRD t WHRL t t QVVL F 27 ...
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... AT49LL080 Ordering Information I (mA) CC Active Standby 67 0.10 32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Plastic Thin Small Outline Package, Type I (TSOP) AT49LL080 28 Ordering Code Package AT49LL080-33JC AT49LL080-33TC Package Type Operation Range 32J Extended Commercial 40T ( 3273C–FLASH–5/03 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3273C–FLASH–5/03 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) AT49LL080 0.318(0.0125) 0.191(0.0075 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 3.175 – ...
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... This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LL080 30 PIN SEATING PLANE ...
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... Atmel Corporation 2003. All rights reserved. Atmel trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 ...