AT28HC256N-12JI ATMEL [ATMEL Corporation], AT28HC256N-12JI Datasheet - Page 3

• Manufacturer Part Number: AT28HC256N-12JI
• Description: 256 (32K x 8) High-speed Parallel EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

Device Operation
3446B–PEEPR–4/04
READ: The AT28HC256N is accessed like a Static RAM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state when either
CE or OE is high. This dual-line control gives designers flexibility in preventing bus con-
tention in their system.
BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and
OE high initiates a write cycle. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a
byte write has been started it will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration of t
effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28HC256N allows 1 to 64 bytes of
data to be written into the device during a single internal programming period. A page
write operation is initiated in the same manner as a byte write; the first byte written can
then be followed by 1 to 63 additional bytes. Each successive byte must be written
within 150 µs (t
will cease accepting data and commence the internal programming operation. All bytes
during a page write operation must reside on the same page as defined by the state of
the A6 - A14 inputs. That is, for each WE high to low transition during the page write
operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written.
The bytes may be loaded in any order and may be altered within the same load period.
Only bytes which are specified for writing will be written; unnecessary cycling of other
bytes within the page does not occur.
DATA POLLING: The AT28HC256N features DATA Polling to indicate the end of a
write cycle. During a byte or page write cycle an attempted read of the last byte written
will result in the complement of the written data to be presented on I/O
cycle has been completed, true data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write cycle.
TOGGLE BIT: In addition to DATA Polling the AT28HC256N provides another method
for determining the end of a write cycle. During the write operation, successive attempts
to read data from the device will result in I/O
write has completed, I/O
bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes to any 5-volt-only
nonvolatile memory may occur during transition of the host system power supply. Atmel
has incorporated both hardware and software features that will protect the memory
against inadvertent writes.
HARDWARE PROTECTION: Hardware features protect against inadvertent writes to
the AT28HC256N in the following ways: (a) V
the write function is inhibited; (b) V
device will automatically time out 5 ms typical) before allowing a write; (c) write inhibit –
holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter
– pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled data protection feature has
been implemented on the AT28HC256N. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by
the user; the AT28HC256N is shipped from Atmel with SDP disabled.
BLC
) of the previous byte. If the t
6
will stop toggling and valid data will be read. Testing the toggle
CC
power-on delay – once V
6
toggling between one and zero. Once the
CC
BLC
sense – if V
limit is exceeded the AT28HC256N
AT28HC256N
CC
CC
WC
is below 3.8V (typical)
, a read operation will
has reached 3.8V the
7
. Once the write
3