W25Q16 WINBOND [Winbond], W25Q16 Datasheet
W25Q16
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W25Q16 Summary of contents
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... AND 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 - Preliminary - Revision B ...
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... Block Protect Bits (BP2, BP1, BP0)..............................................................................12 10.1.4 Top/Bottom Block Protect (TB).....................................................................................12 10.1.5 Sector/Block Protect (SEC) ..........................................................................................12 10.1.6 Status Register Protect (SRP1, SRP0).........................................................................13 10.1.7 Quad Enable (QE) ........................................................................................................13 10.1.8 Status Register Memory Protection ..............................................................................15 10.2 INSTRUCTIONS........................................................................................................... 18 10.2.1 Manufacturer and Device Identification ........................................................................18 10.2.2 Instruction Set Table 1..................................................................................................19 10.2.3 Instruction Set Table 2 (Read Instructions) ..................................................................20 W25Q80, W25Q16, W25Q32 Table of Contents - 2 - ...
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... Endurance and Data Retention .................................................................................... 47 11.4 Power-up Timing and Write Inhibit Threshold .............................................................. 47 11.5 DC Electrical Characteristics ........................................................................................ 48 11.6 AC Measurement Conditions........................................................................................ 49 11.7 AC Electrical Characteristics ........................................................................................ 50 11.8 AC Electrical Characteristics (cont’d) ........................................................................... 51 11.9 Serial Output Timing ..................................................................................................... 52 11.10 Input Timing................................................................................................................. 52 11.11 Hold Timing ................................................................................................................. 52 12. PACKAGE SPECIFICATION .................................................................................................... 53 W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 3 - Preliminary - Revision B ...
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... SOIC 208-mil (Package Code SS)...................................................................... 53 12.2 8-Pin PDIP 300-mil (Package Code DA) ...................................................................... 54 12.3 8-contact 6x5 WSON (Package Code ZP) ................................................................... 55 12.4 8-contact 6x5 WSON Cont’d. ....................................................................................... 56 12.5 16-Pin SOIC 300-mil (Package Code SF) .................................................................... 57 13. ORDERING INFORMATION .................................................................................................... 58 13.1 Valid Part Numbers and Top Side Marking .................................................................. 59 14. REVISION HISTORY ................................................................................................................ 60 W25Q80, W25Q16, W25Q32 - 4 - ...
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... GENERAL DESCRIPTION The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data ...
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... PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q80, W25Q16, W25Q32 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q80, W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP) 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM PIN NO. PIN NAME 1 /CS ...
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... PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q16 and W25Q32 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N (IO1) 9 /WP (IO2) 10 GND 11 N/C 12 N/C 13 N (IO0) 16 CLK *1 IO0 and IO1 are used for Dual and Quad instructions *2 IO0 – ...
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... W25Q80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON (package code ZP). W25Q16 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON as shown in figure 1a, and 1b, respectively. The W25Q16 and W25Q32 are offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet ...
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... BLOCK DIAGRAM Figure 2. W25Q80, W25Q16 and W25Q32 Block Diagram W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 9 - Preliminary - Revision B ...
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... CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the W25Q80, W25Q16, W25Q32 - 10 - ...
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... Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. W25Q80, W25Q16, W25Q32 (1) (1) time delay is reached. If needed a pull-up resister on /CS can ...
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... The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. W25Q80, W25Q16, W25Q32 , and Characteristics). When the program, erase or write status characteristics) ...
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... QE pin is set the Quad IO2 and IO3 pins are enabled. WARNING: The QE bit should never be set during standard SPI or Dual SPI operation if the /WP or /HOLD pins are tied directly to the power supply or ground. W25Q80, W25Q16, W25Q32 Description /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1 ...
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... W25Q80, W25Q16, W25Q32 Figure 3a. Status Register-1 Figure 3b. Status Register ...
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... X W25Q80, W25Q16, W25Q32 W25Q32 (32M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 63 3F0000h - 3FFFFFh 62 and 63 3E0000h - 3FFFFFh 60 thru 63 3C0000h - 3FFFFFh 56 thru 63 380000h - 3FFFFFh 48 thru 63 300000h - 3FFFFFh 32 thru 63 200000h - 3FFFFFh 0 000000h - 00FFFFh 0 and 1 ...
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... X W25Q80, W25Q16, W25Q32 W25Q16 (16M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 31 1F0000h - 1FFFFFh 30 and 31 1E0000h - 1FFFFFh 28 thru 31 1C0000h - 1FFFFFh 24 thru 31 180000h - 1FFFFFh 16 thru 31 100000h - 1FFFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh 0 thru 3 000000h - 03FFFFh ...
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... X Note don’t care W25Q80, W25Q16, W25Q32 W25Q80 (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 15 0F0000h - 0FFFFFh 14 and 15 0E0000h - 0FFFFFh 12 thru 15 0C0000h - 0FFFFFh 8 thru 15 080000h - 0FFFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh 0 thru 3 ...
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... Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 10.2.1 Manufacturer and Device Identification MANUFACTURER ID Winbond Serial Flash Device ID Instruction W25Q80 W25Q16 W25Q32 W25Q80, W25Q16, W25Q32 (M7-M0) EFh (ID15-ID0) (ID7-ID0) 9Fh ABh, 90h 4014h 13h 4015h ...
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... This instruction is recommended when using the Dual or Quad Mode bit feature. See section 10.2.28 for more information. 5. The Device ID will repeat continuously until /CS terminates the instruction. 6. See Manufacturer and Device Identification table for Device ID information. 7. This feature is available upon special order. Please contact Winbond for details. W25Q80, W25Q16, W25Q32 (1) BYTE 2 BYTE 3 (2) (S7– ...
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... IO3 = A23, A19, A15, A11, A7, A3, M7 Fast Read Quad I/O Data IO0 = ( D4, D0, …..) IO1 = ( D5, D1, …..) IO2 = ( D6, D2, …..) IO3 = ( D7, D3, …..) W25Q80, W25Q16, W25Q32 BYTE 2 BYTE 3 A23–A16 A15–A8 A23–A16 A15– ...
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... DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 5. Write Disable Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 21 - Preliminary - Revision B ...
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... Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 - 22 - ...
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... Write Protect (/WP) pin, Lock out or OTP features to disable writes to the status register. Please refer to 10.1.16 for detailed descriptions regarding Status Register protection methods. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 23 - (See AC ...
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... If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f Electrical Characteristics). W25Q80, W25Q16, W25Q32 Figure 8. Read Data Instruction Sequence Diagram - 24 - (see AC ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. W25Q80, W25Q16, W25Q32 (see AC Electrical Characteristics). This is accomplished by adding R Figure 9 ...
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... The input data during the dummy clocks is “don’t care”. However, the IO out clock. Figure 10. Fast Read Dual Output Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 and IO . This allows data to be transferred from the 0 ...
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... The input data during the dummy clocks is “don’t care”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. Figure 11. Fast Read Quad Output Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 , and IO ...
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... A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 for detailed descriptions). Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh) W25Q80, W25Q16, W25Q32 - 28 - ...
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... Figure 12b. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = Axh W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 Preliminary - Revision B ...
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... A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 for detailed descriptions). Figure 13a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh) W25Q80, W25Q16, W25Q32 , ...
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... W25Q80, W25Q16, W25Q32 Figure 13b. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = Axh Publication Release Date: September 26, 2007 Preliminary - Revision B ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 14. Page Program Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 - 32 - ...
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... All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 15. Figure 15. Quad Input Page Program Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 , and IO ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 16. Sector Erase Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 (See AC Characteristics). While the Sector Erase ...
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... BP0) bits (see Status Register Memory Protection table). Figure 17. 32KB Block Erase Instruction Sequence Diagram Note: For W25Q16, user should not issue 32KB Block Erase (52h) instruction to the top or bottom 32KB block when SEC bit in Status Register is set to “1”. W25Q80, W25Q16, W25Q32 1 (See AC Characteristics) ...
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... BP0) bits (see Status Register Memory Protection table). Figure 18. 64KB Block Erase Instruction Sequence Diagram Note: For W25Q16, user should not issue 64KB Block Erase (D8h) instruction to the top or bottom 64KB block when SEC bit in Status Register is set to “1”. W25Q80, W25Q16, W25Q32 (See AC Characteristics) ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 19. Chip Erase Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 (See AC Characteristics). While the Chip Erase cycle Publication Release Date: September 26, 2007 ...
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... Erase Suspend. After issued the BUSY bit in the status register will be set and the sector or block will complete the erase operation. Resume instructions will be ignored unless an Erase Suspend operation is active. W25Q80, W25Q16, W25Q32 Figure 20. Erase Suspend Instruction Sequence Figure 21. Erase Resume Instruction Sequence ...
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... Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 22. Deep Power-down Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 39 - Preliminary - Revision B ...
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... ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 25. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high ...
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... Figure 24. Release Power-down/High Performance Mode Instruction Sequence Figure 25. Release Power-down / Device ID Instruction Sequence Diagram W25Q80, W25Q16, W25Q32 (See AC Characteristics). After this time duration the device will RES2 Publication Release Date: September 26, 2007 ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 26. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Read Unique ID Number The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q80, W25Q16 or W25Q64 device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks ...
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... Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. For memory type and capacity values refer to Manufacturer and Device Identification table. W25Q80, W25Q16, W25Q32 Figure 28. Read JEDEC ...
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... Figure 29. Mode Bit Reset for Fast Read Dual/Quad I/O To reset Mode Bit during Quad I/O operation, only eight clocks are needed. The instruction is “FFh”. To reset Mode Bit during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh”. W25Q80, W25Q16, W25Q32 Mode Bit Reset Mode Bit Reset ...
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... SYMBOL Supply Voltage VCC (1) Ambient Temperature, T Operating Note: 1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage. W25Q80, W25Q16, W25Q32 (1) SYMBOL CONDITIONS VCC V Relative to Ground IO <20nS Transient V IOT Relative to Ground ...
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... Data Retention 55°C 11.4 Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. W25Q80, W25Q16, W25Q32 CONDITIONS SYMBOL MIN t (1) VSL t (1) PUW ...
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... Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V. 2. Checker Board Pattern. W25Q80, W25Q16, W25Q32 CONDITIONS MIN ( ( OUT /CS = VCC, VIN = GND or VCC ...
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... AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. W25Q80, W25Q16, W25Q32 SYMBOL Figure 31 ...
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... Deselect Time (for Array Read Read / Erase or Program Read Status Registers) Output Disable Time Clock Low to Output Valid 2.7V-3.6V / 3.0V-3.6V Clock Low to Output Valid (for Read ID instructions) 2.7V-3.6V / 3.0V-3.6V Output Hold Time /HOLD Active Setup Time relative to CLK W25Q80, W25Q16, W25Q32 SYMBOL ALT CLH ...
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... Page Program Time Sector Erase Time (4KB) Block Erase Time (32KB) Block Erase Time (64KB) Chip Erase Time W25Q80 Chip Erase Time W25Q16 Chip Erase Time W25Q32 Notes: 1. Clock high + Clock low must be less than or equal to 1/f 2. Value guaranteed by design and/or characterization, not 100% tested in production. ...
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... Serial Output Timing 11.10 Input Timing 11.11 Hold Timing W25Q80, W25Q16, W25Q32 - 52 - ...
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... BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. W25Q80, W25Q16, W25Q32 MILLIMETERS INCHES ...
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... A 0.125 2 B 0.016 B 0.058 1 c 0.008 D E 0.290 E 0.245 1 e 0.090 1 L 0.120 α e 0.335 A S W25Q80, W25Q16, W25Q32 A Base Plane 1 Seating Plane Dimension in inch Dimension in mm Nom Nom Min Max Min Max 0.175 4.45 0.25 0.130 0.135 3.18 3.30 3.43 0.018 0.022 0.41 0.46 0.56 0.060 1.47 1 ...
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... WSON (Package Code ZP) W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 55 - Preliminary - Revision B ...
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... WSON Cont’d. W25Q80, W25Q16, W25Q32 - 56 - ...
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... E1 ( θ y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. W25Q80, W25Q16, W25Q32 MILLIMETERS INCHES MIN MAX MIN 2.36 2.64 0.093 0.10 ...
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... Only the 2 letter is used for the part marking. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. 1c. The “W” prefix is not included on the part marking. W25Q80, W25Q16, W25Q32 ( ...
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... PACKAGE TYPE DENSITY 8M-bit SS 16M-bit SOIC-8 208mil 32M-bit 16M-bit SF SOIC-16 300mil 32M-bit 8M-bit ZP WSON-8 6x5mm 16M-bit W25Q80, W25Q16, W25Q32 PRODUCT NUMBER TOP SIDE MARKING W25Q80VSSIG W25Q16VSSIG W25Q32VSSIG W25Q16VSFIG W25Q32VSFIG W25Q80VZPIG W25Q16VZPIG Publication Release Date: September 26, 2007 - 59 - 25Q80VSIG 25Q16VSIG 25Q32VSIG 25Q16VFIG ...
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... Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. W25Q80, W25Q16, W25Q32 PAGE New Create Advanced Figures 2, 3A-B, 13A–14C, 16, 24, 25 Table 10 ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W25Q80, W25Q16, W25Q32 Important Notice Publication Release Date: September 26, 2007 - 61 - ...