AT26DF321-S3U ATMEL [ATMEL Corporation], AT26DF321-S3U Datasheet
AT26DF321-S3U
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AT26DF321-S3U Summary of contents
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... SOIC (200-mil wide) – 16-lead SOIC (300-mil wide) 1. Description The AT26DF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...
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... Specifically designed for use in 3-volt systems, the AT26DF321 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...
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... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF321 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...
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... Sector Protection Block Erase Function (D8h Command) (52h Command) 64KB 64KB (Sector 63) 64KB 64KB (Sector 62) 64KB 64KB (Sector 0) AT26DF321 [Preliminary] 4 Block Erase Detail 32KB 4KB Block Address Block Erase Block Erase Range (20h Command) 4KB 3FFFFFh – 3FF000h 3FEFFFh – 3FE000h ...
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... SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT26DF321 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...
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... Unprotect Sector Global Protect/Unprotect Read Sector Protection Registers Status Register Commands Read Status Register Write Status Register Miscellaneous Commands Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down AT26DF321 [Preliminary] 6 Opcode Address Bytes 0Bh 0000 1011 3 03h 0000 0011 3 20h ...
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... OPCODE ADDRESS BITS A23- MSB MSB HIGH-IMPEDANCE AT26DF321 [Preliminary DON'T CARE DATA BYTE ...
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... For faster throughput recommended that the Status Register be polled rather than waiting the t some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. AT26DF321 [Preliminary] 8 time to determine if the data bytes have finished programming ...
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... MSB ADDRESS BITS A23-A0 DATA IN BYTE MSB MSB AT26DF321 [Preliminary DATA MSB DATA IN BYTE ...
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... For faster throughput recommended that the Status Regis- ter be polled rather than waiting the t some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. AT26DF321 [Preliminary] 10 time to determine if the device has finished erasing. At BLKE ...
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... Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. 3633C–DFLASH–08/06 AT26DF321 [Preliminary] Chip Erase ...
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... Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the Sector Protection Register corresponding to the physical sector addressed by A23- A0 will be set to the logical “1” state, and the sector itself will then be protected from program AT26DF321 [Preliminary] 12 Write Disable ...
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... SCK OPCODE MSB HIGH-IMPEDANCE SO for more details). If the Sector Protection Registers are locked, then any attempts to AT26DF321 [Preliminary] “Status Register Commands” ADDRESS BITS A23- ...
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... Status Register. Conversely, to per- form a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT26DF321 [Preliminary] 14 Unprotect Sector CS ...
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... SPRL bit can be changed back from a 1 since the WP ↕ pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from AT26DF321 [Preliminary] New SPRL Value ...
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... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (please refer to AT26DF321 [Preliminary] 16 for details on the Status Register format and what values can be Read Sector Protection Register – ...
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... When changing the SPRL bit to a logical “1” from a logical “0” also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits and 2 of the Status Register. 3633C–DFLASH–08/06 AT26DF321 [Preliminary] Read Sector Protection Register 0 1 ...
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... The tables below detail the various protection and locking states of the device. Table 9-4. WP (Don't Care) Note: Table 9- AT26DF321 [Preliminary] 18 Software Protection Register States Sector Protection Register ( “n” represents a sector number Hardware and Software Locking SPRL ...
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... RDY/BSY Ready/Busy Status Notes: 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command. 2. R/W = Readable and writeable R = Readable only 3633C–DFLASH–08/06 AT26DF321 [Preliminary] (2) Type Description 0 Sector Protection Registers are unlocked (default). R/W 1 Sector Protection Registers are locked. ...
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... Write Status Register operation completes successfully or aborts • Protect Sector operation completes successfully or aborts • Unprotect Sector operation completes successfully or aborts • Byte/Page Program operation completes successfully or aborts • Block Erase operation completes successfully or aborts • Chip Erase operation completes successfully or aborts AT26DF321 [Preliminary] 20 3633C–DFLASH–08/06 ...
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... SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. 3633C–DFLASH–08/06 AT26DF321 [Preliminary ...
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... Table 11-1. Manufacturer and Device ID Information Byte No. Data Type 1 Manufacturer ID 2 Device ID (Part 1) 3 Device ID (Part 2) 4 Extended Device Information String Length AT26DF321 [Preliminary] 22 Write Status Register Format Bit 6 Bit 5 Bit 4 X Global Protect/Unprotect ...
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... OPCODE SI 9Fh HIGH-IMPEDANCE 1Fh MANUFACTURER ID Note: Each transition shown for SI and SO represents one byte (8 bits) AT26DF321 [Preliminary] Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT26DFxxx series) 47h Density Code: 00111 (32-Mbit) ...
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... Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, then the device will abort the operation and return to the Deep Power-Down mode. Figure 11-3. Resume from Deep Power-Down AT26DF321 [Preliminary ...
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... Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 3633C–DFLASH–08/06 AT26DF321 [Preliminary] *NOTICE: + 0.5V CC Ind. Condition CS all inputs at CMOS levels CS VCC, all inputs at CMOS levels MHz mA, OUT ...
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... Page Program Time (256 Bytes Byte Program Time BP t Block Erase Time BLKE (1) t Chip Erase Time CHPE (1) t Write Status Register Time WRSR Notes: 1. Not 100% tested (value guaranteed by design and characterization). AT26DF321 [Preliminary] 26 Min 6.8 6.8 0.1 0 100 Min Typ 1 ...
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... Power-Up Conditions Parameter Minimum V to Chip Select Low Time CC Power-up Device Delay Before Program or Erase Allowed Power-On Reset Voltage 12.7 Input Test Waveforms and Measurement Levels 12.8 Output Test Load 3633C–DFLASH–08/06 AT26DF321 [Preliminary] 2.4V AC DRIVING 1.5V LEVELS 0.45V < (10 DEVICE ...
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... SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO AT26DF321 [Preliminary CSLH t t SCKH SCKL t DH LSB WPH LSB OF ...
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... Green Package Options (Pb/Halide-free/RoHS Compliant) f (MHz) Ordering Code SCK 66 AT26DF321-SU 66 AT26DF321-S3U 8S2 8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 16S 16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 3633C–DFLASH–08/06 AT26DF321 [Preliminary] Package 8S2 ...
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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT26DF321 [Preliminary TOP VIEW ...
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... Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side the length of the terminal for soldering to a substrate. 2325 Orchard Parkway San Jose, CA 95131 R 3633C–DFLASH–08/06 AT26DF321 [Preliminary TITLE 16S, 16-lead, 0.300" ...
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... Changed description of bit 5 in Table 10-1 undefined. Removed MLF package offerings. Added 8-lead SOIC (200-mil wide) package. Changed ordering code for 16-lead SOIC from AT26DF321-SU to AT26DF321-S3U. Added errata regarding Chip Erase. from “0” to “x” and specified that the value is 3633C–DFLASH–08/06 ...
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... Use the Block Erase (4KB, 32KB, or 64KB) commands as an alternative. The Block Erase func- tion is not affected by the Chip Erase issue. 17.1.3 Resolution The Chip Erase feature is being fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. 3633C–DFLASH–08/06 AT26DF321 [Preliminary] 33 ...
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... Atmel Corporation. All rights reserved. Atmel istered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...