AT26F004-SSU ATMEL [ATMEL Corporation], AT26F004-SSU Datasheet - Page 5

• Manufacturer Part Number: AT26F004-SSU
• Description: 4-megabit 2.7-volt Only Serial Firmware DataFlash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

5. Device Operation
6. Commands and Addressing
3588A–DFLSH–10/05
The AT26F004 is controlled by a set of instructions that are sent from a host controller, com-
monly referred to as the SPI Master. The SPI Master communicates with the AT26F004 via the
SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26F004 supports the two most common modes, SPI modes
0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal when
in the inactive state (when the SPI Master is in standby mode and not transferring any data).
With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always output
on the falling edge of SCK.
Figure 5-1.
A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.
Following the opcode, instruction dependent information such as address and data bytes would
then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with
the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT26F004 will be ignored by the device and no operation will be
started. The device will continue to ignore any data presented on the SI pin until the start of the
next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-
serted before all eight bits of an opcode are sent to the device, then the device will simply return
to the idle state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23 - A0. Since the upper address limit of the AT26F004 memory array is
07FFFFh, address bits A23 - A19 are always ignored by the device.
SCK
SO
CS
SI
SPI Mode 0 and 3
MSB
LSB
MSB
AT26F004
LSB
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