AT45DB321D ATMEL [ATMEL Corporation], AT45DB321D Datasheet
AT45DB321D
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AT45DB321D Summary of contents
Page 1
... MHz. Its 34,603,008 bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream ...
Page 2
... To allow for simple in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... Ground: The ground reference for the power supply. GND should be connected to the system GND ground. 3597J–DFLASH–4/08 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. CC AT45DB321D Asserted State Type Low Input – Input – ...
Page 4
... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level ...
Page 5
... SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a 3597J–DFLASH–4/08 AT45DB321D Table 15-1 on page 28 through Table 15-7 on ...
Page 6
... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred AT45DB321D 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...
Page 7
... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). 3597J–DFLASH–4/08 specification. The Main Memory Page Read bypasses both data buffers and SCK . The D1H and D3H opcode can be used for lower frequency CAR1 AT45DB321D . CAR2 7 ...
Page 8
... It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register and the RDY/BUSY pin will indicate that the part is busy. AT45DB321D 8 . During this time, EP ...
Page 9
... AT45DB321D PA4/ PA3/ PA2/ PA1/ A13 A12 A11 A10 • • • • ...
Page 10
... The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. Note: AT45DB321D 10 PA8/ PA7/ PA6/ PA5/ ...
Page 11
... Status Register. 3597J–DFLASH–4/08 Chip Erase CS Opcode SI Byte 1 Each transition represents 8 bits 1. Refer to the errata regarding Chip Erase on AT45DB321D Byte 1 Byte 2 Byte 3 C7H 94H 80H Opcode Opcode Opcode Byte 2 ...
Page 12
... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB321D 12 Byte 1 3DH Enable Sector Protection ...
Page 13
... When the WP pin is deasserted; however, the sector protection WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB321D , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
Page 14
... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a (Pages 0-7) Protect Sector 0b (Pages 8-127) Protect Sectors 0a (Pages 0-7), 0b (Pages 8-127) Note: AT45DB321D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Pages 0-7) Bit (1) 1. The default value for bytes 0 through 63 when shipped from Atmel is 00H don’ ...
Page 15
... Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB321D PE Byte 2 Byte 3 Byte 4 2AH 7FH Opcode Opcode Byte 3 Byte 4 Section 9.1, the Sector Protection Register , during ...
Page 16
... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Byte 1 ...
Page 17
... Instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. 3597J–DFLASH–4/ Dummy Byte AT45DB321D Byte 1 Byte 2 Byte 3 32H xxH xxH Data Byte ...
Page 18
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes ...
Page 19
... Each transition represents 8 bits 3597J–DFLASH–4/08 Sector 0 (0a, 0b) (Pages 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB321D 0 (0a, 0b) See Below 0a 0b (Pages 8-127) Bit 5, 4 Bit ...
Page 20
... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
Page 21
... CS pin transitions from a low to a high state. Dur- ing the transfer of a page of data (t monitored to determine whether the transfer has been completed. 3597J–DFLASH–4/ Data Byte n ), the status register can be read or the RDY/BUSY can be XFR AT45DB321D Data Byte Data Byte ...
Page 22
... AT45DB321D 22 ), the status register and the RDY/BUSY pin will indicate that COMP Figure 25-1 (page 45) is recommended ...
Page 23
... The device density is indicated using bits and 2 of the status register. For the AT45DB321D, the four bits are 1101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 24
... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB321D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
Page 25
... Figure 13-1. Erase Sector Protection Register 3597J–DFLASH–4/08 Section , during which time the Status Register will indicate that the device Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB321D Section 26. ”Ordering Information” on 13.1). Byte 1 Byte 2 Byte 3 3DH 2AH 80H Opcode Opcode Byte 3 Byte 4 ...
Page 26
... Bit 4 00H 14.1.4 Byte 4 – Extended Device Information String Length Byte Count Hex Value Bit 7 Bit 6 Bit 5 Bit 4 00H AT45DB321D 26 Bit 3 Bit 2 Bit 1 Bit Density Code Bit 3 Bit 2 Bit 1 Bit Product Version Code Bit 3 ...
Page 27
... Manufacturer ID Device ID Device ID Extended Byte 1 Byte 2 Byte 3 Device Information String Length AT45DB321D Data Data Extended Extended Device Device Information Information Byte x Byte This information would only be output if the Extended Device Information String Length value was something other than 00H. ...
Page 28
... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB321D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
Page 29
... Note: 3597J–DFLASH–4/08 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB321D Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H 3DH + 2AH + 7FH + 30H ...
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... D7h E8h Notes Don’t Care AT45DB321D 30 Address Byte Address Byte ...
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... N/A N Don’t Care AT45DB321D Address Byte ...
Page 32
... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB321D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
Page 33
... MHz mA; OUT CMOS levels CMOS levels I 1 -100 µ AT45DB321D AT45DB321D -40° 85° C 2.7V to 3.6V Min Typ Max 0 0.7 0.4 - 0.2V Units µA µA ...
Page 34
... Page Erase Time (512/528 bytes Block Erase Time (4,096/4,224 bytes Chip Erase Time CE t Sector Erase Time (262,144/270,336 bytes RESET Pulse Width RST t RESET Recovery Time REC AT45DB321D 34 AT45DB321D Min Typ Max 6.8 6.8 0.1 0 100 ...
Page 35
... MHz) of the RapidS serial case. 3597J–DFLASH–4/08 2.4V AC DRIVING 1.5V LEVELS 0.45V DEVICE UNDER TEST 30 pF period. These timing waveforms are valid over the full frequency range (max- WL AT45DB321D AC MEASUREMENT LEVEL page 36. Waveform 1 shows the SCK signal being ). Timing waveforms 1 and 2 conform ...
Page 36
... Waveform 2 – SPI Mode 3 Compatible (for frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB321D CSS VALID OUT VALID ...
Page 37
... Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. 3597J–DFLASH–4/08 ™ Function LSB BYTE-MOSI AT45DB321D MSB BYTE- LSB 37 ...
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... Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB Don’t Care 21.8 Command Sequence for Read/Write Operations for Page Size 528 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB321D 38 CMD 8 bits 8 bits 8 bits Page Address ...
Page 39
... BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 X BFA7-0 X···X, BFA9-8 Starts self-timed erase/program operation BINARY PAGE SIZE A21- DON'T CARE BITS CMD PA12-6 AT45DB321D BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (512/528 BYTES) BUFFER 2 WRITE Completes writing into selected buffer n n+1 ...
Page 40
... BUFFER 1 23.1 Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB321D 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A21-A16 A7-A0 ...
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... ADDRESS BITS A21 - MSB MSB AT45DB321D BFA7 Dummy Byte (opcodes D1H and D3H) 1 Dummy Byte (opcodes D4H and D6H DATA BYTE ...
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... MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB321D OPCODE ADDRESS BITS A21- MSB ...
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... MSB OPCODE DON'T CARE MSB AT45DB321D DATA BYTE MSB MSB ...
Page 44
... CS 0 SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB321D OPCODE DON'T CARE ...
Page 45
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3597J–DFLASH–4/08 START provide address (82H, 85H) END AT45DB321D and data BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) ...
Page 46
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB321D 46 START ...
Page 47
... AT45DB321D-MU-SL955 AT45DB321D-MWU (3) AT45DB321D-MWU-SL954 (4) AT45DB321D-MWU-SL955 AT45DB321D-SU (3) AT45DB321D-SU-SL954 (4) AT45DB321D-SU-SL955 AT45DB321D-TU Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 528 bytes. The user is able to configure these parts to a 512-byte page size if desired. ...
Page 48
... Packaging Information 27.1 8M1-A – MLF (VDFN BOTTOM VIEW 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321D Pin 1 ID TOP VIEW A2 A 0.45 D2 Pin #1 Notch (0. TITLE 8M1-A, 8-pad 1.00 mm Body, Very Thin Dual Flat Package No Lead (MLF) SIDE VIEW ...
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... San Jose, CA 95131 R 3597J–DFLASH–4/08 1 Option A Pin #1 Chamfer (C 0.30) Option B e Pin #1 K Notch (0.20 R) TITLE 8MW, 8-pad 1.0 mm Body, Very Thin Dual Flat Package No Lead (MLF) AT45DB321D SIDE VIEW A1 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 – – b 0.35 ...
Page 50
... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321D TOP VIEW ...
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... Orchard Parkway San Jose, CA 95131 R 3597J–DFLASH–4/08 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) AT45DB321D 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – ...
Page 52
... Changed the Product Version Code to 00001. Corrected typographical errors. Added errata regarding Chip Erase. Added AT45DB321D-SU to ordering information and corresponding 8S2 package. Removed “not recommended for new designs” note from ordering information for 8MW package. Added AT45DB321D-CNU to ordering information and corresponding 8CN3 package. Removed “ ...
Page 53
... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 29.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. 3597J–DFLASH–4/08 AT45DB321D 53 ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...